Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.

Abstract: Disclosed are a semiconductor package and a manufacturing method of a semiconductor package. In one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, a first encapsulant, at least one heat dissipation element and a second encapsulant. The plurality of semiconductor dies are disposed on the interposer substrate. The first encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies. The at least one heat dissipation element is disposed on the plurality of semiconductor dies. The second encapsulant is disposed on the first encapsulant and surrounds the at least one heat dissipation element.

Abstract: A method of forming a semiconductor structure includes: forming a first redistribution structure on a first side of a wafer, the first redistribution structure including dielectric layers and conductive features in the dielectric layers; forming grooves in the first redistribution structure, the grooves exposing sidewalls of the dielectric layers and the wafer, the grooves defining a plurality of die attaching regions; bonding a plurality of dies to the first redistribution structure in the plurality of die attaching regions; forming a first molding material on the first side of the wafer around the plurality of dies, the first molding material filling the grooves; forming a passivation layer on a second side of the wafer opposing the first side; and dicing along the grooves from the second side of the wafer to form a plurality of individual semiconductor packages, each of the plurality of individual semiconductor packages including a respective die.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.

Abstract: A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

Abstract: A touch electrode is provided in the disclosure, including a first electrode layer and a second electrode layer. The first electrode layer includes a plurality of first electrodes. Each of the first electrodes includes a plurality of first electrode wires and a plurality of first axis wires, in which each of the first axis wires is connected to and perpendicular to the first electrode wires. The second electrode layer is electrically insulated and located above or beneath the first electrode layer. The second electrode layer includes a plurality of second electrodes. Each of the second electrodes includes a plurality of second electrode wires, and the second electrodes are spaced apart from each other and connected to each other in parallel. The material of the first and the second electrode layers is metal nanowires. A touch panel and a touch display, including the touch electrode described herein, are also provided.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

Abstract: A method for forming a semiconductor package structure includes stacking chips to form a chip stack over an interposer. The method also includes disposing a semiconductor die over the interposer. The method also includes filling a first encapsulating layer between the chips and surrounding the chip stack and the semiconductor die. The method also includes forming a second encapsulating layer covering the chip stack and the semiconductor die. The first encapsulating layer fills the gap between the chip stack and the semiconductor die.

Abstract: A touch electrode is provided in the disclosure, including a first electrode layer and a second electrode layer. The first electrode layer includes a plurality of first electrodes. Each of the first electrodes includes a plurality of first electrode wires and a plurality of first axis wires, in which each of the first axis wires is connected to and perpendicular to the first electrode wires. The second electrode layer is electrically insulated and located above or beneath the first electrode layer. The second electrode layer includes a plurality of second electrodes. Each of the second electrodes includes a plurality of second electrode wires, and the second electrodes are spaced apart from each other and connected to each other in parallel. The material of the first and the second electrode layers is metal nanowires. A touch panel and a touch display, including the touch electrode described herein, are also provided.

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

Abstract: A method for forming a semiconductor package structure includes stacking chips to form a chip stack over an interposer. The method also includes disposing a semiconductor die over the interposer. The method also includes filling a first encapsulating layer between the chips and surrounding the chip stack and the semiconductor die. The method also includes forming a second encapsulating layer covering the chip stack and the semiconductor die. The first encapsulating layer fills the gap between the chip stack and the semiconductor die.

Abstract: The installation position pointer system comprises a laser source to supply a laser beam, a driving device to align the laser beam, a controller device to control the operation of the driving device in accordance with an installation position data (IPD) of an attachment to be installed in a building and an associated reference position in the building, and an input device to obtain the IPD of a plurality of attachments from the attachment. The IPD of the attachments may be provided by an attachment installation position database system.

Abstract: An indoor positioning system based on building design information is disclosed. The system includes a server computer to provide indoor position information relating to a building, a plurality of beacons to be installed in selected locations in the building and to broadcast by each beacon an indoor position message indicating the indoor position of the beacon, and an installer to configure the beacons with their corresponding indoor position information. An indoor positioning system development system is also provided. The development system incorporates building information files and provides a development interface for users to determine respective locations to install the beacons. Once completed, the obtained results are converted into an indoor position message for each beacon and configured in the corresponding beacon.

Abstract: A structure of a thermoelectric module including at least one substrate, a thermoelectric device and an insulation protection structure is provided. The thermoelectric device is disposed on the substrate. The insulation protection structure surrounds the thermoelectric device. The thermoelectric device includes at least three electrode plates, first type and second type thermoelectric materials and a diffusion barrier structure. First and second electrode plates among the three electrode plates are disposed on the substrate. The first type thermoelectric material is disposed on the first electrode plate. The second type thermoelectric material is disposed on the second electrode plate. A third electrode plate among the three electrode plates is disposed on the first type and second type thermoelectric materials. The diffusion barrier structure is disposed on two terminals of each of the first type and second type thermoelectric materials.

Abstract: An indoor positioning system based on building design information is disclosed. The system includes a server computer to provide indoor position information relating to a building, a plurality of beacons to be installed in selected locations in the building and to broadcast by each beacon an indoor position message indicating the indoor position of the beacon, and an installer to configure the beacons with their corresponding indoor position information. An indoor positioning system development system is also provided. The development system incorporates building information files and provides a development interface for users to determine respective locations to install the beacons. Once completed, the obtained results are converted into an indoor position message for each beacon and configured in the corresponding beacon.

Abstract: A structure of a thermoelectric module including at least one substrate, a thermoelectric device and an insulation protection structure is provided. The thermoelectric device is disposed on the substrate. The insulation protection structure surrounds the thermoelectric device. The thermoelectric device includes at least three electrode plates, first type and second type thermoelectric materials and a diffusion barrier structure. First and second electrode plates among the three electrode plates are disposed on the substrate. The first type thermoelectric material is disposed on the first electrode plate. The second type thermoelectric material is disposed on the second electrode plate. A third electrode plate among the three electrode plates is disposed on the first type and second type thermoelectric materials. The diffusion barrier structure is disposed on two terminals of each of the first type and second type thermoelectric materials.