Patents by Inventor Cheng-Chieh Tsai
Cheng-Chieh Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379814Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
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Publication number: 20240379259Abstract: An extreme ultra violet (EUV) light source apparatus includes an excitation laser inlet port configured to receive an excitation laser, and a first mirror configured to reflect the excitation laser that passes through a zone of excitation. A metal droplet is irradiated by the excitation laser.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Hung TSAI, Sheng-Kang YU, Shang-Chieh CHIEN, Heng-Hsin LIU, Li-Jui CHEN
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Patent number: 12142663Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.Type: GrantFiled: July 24, 2023Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
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Publication number: 20240369759Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: ApplicationFiled: July 16, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20240363396Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature. The gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12132024Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.Type: GrantFiled: August 29, 2021Date of Patent: October 29, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Tzuan-Horng Liu, Cheng-Chieh Hsieh, Tsung-Yuan Yu
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Publication number: 20240353765Abstract: Microwave heating of debris collecting vanes within the source vessel of a lithography apparatus is used to accomplish uniform temperature distribution in order to reduce fall-on contamination and formation of clogs on the inner and outer surfaces of the vanes.Type: ApplicationFiled: July 1, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Hung TSAI, Sheng-Kang YU, Shang-Chieh CHIEN, Heng-Hsin LIU, Li-Jui CHEN
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Publication number: 20240345491Abstract: A system for monitoring and controlling an EUV light source includes a first temperature sensor, a signal processor, and a process controller. The first temperature sensor includes a portion inserted into a space surrounded by a plurality of vanes through a vane of the plurality of vanes, and obtains an ambient temperature that decreases with time as a function of tin contamination coating on the inserted portion. The signal processor determines an excess tin debris deposition on the vane based on the obtained chamber ambient temperature. The process controller activates a vane cleaning action upon being informed of the excess tin debris deposition by the signal processor, thereby improving availability of the EUV light source tool and reducing risks of tin pollution on other tools such as a reticle.Type: ApplicationFiled: April 12, 2023Publication date: October 17, 2024Inventors: Cheng Hung TSAI, Sheng-Kang Yu, Heng-Hsin Liu, Li-Jui Chen, Shang-Chieh Chien
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Publication number: 20240345493Abstract: A photolithographic apparatus includes a droplet generator, a droplet generator maintenance system, and a controller communicating with the droplet generator maintenance system. The droplet generator maintenance system operatively communicates with the droplet generator, a coolant distribution unit, a gas supply unit, and a supporting member. The gas supply unit includes a heat exchange assembly and an air heating assembly. The coolant distribution unit is configured to control the temperature of the droplet generator within the acceptable droplet generator range.Type: ApplicationFiled: June 27, 2024Publication date: October 17, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Huan CHEN, Cheng-Hsuan WU, Ming-Hsun TSAI, Shang-Chieh CHIEN, Li-Jui CHEN
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Patent number: 12119129Abstract: An extreme ultra violet (EUV) light source apparatus includes a metal droplet generator, a collector mirror, an excitation laser inlet port for receiving an excitation laser, a first mirror configured to reflect the excitation laser that passes through a zone of excitation, and a second mirror configured to reflect the excitation laser reflected by the first mirror.Type: GrantFiled: March 13, 2023Date of Patent: October 15, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng Hung Tsai, Sheng-Kang Yu, Shang-Chieh Chien, Heng-Hsin Liu, Li-Jui Chen
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Patent number: 12105323Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: GrantFiled: July 25, 2023Date of Patent: October 1, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20240321765Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.Type: ApplicationFiled: June 6, 2024Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
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Publication number: 20240320706Abstract: A terminal includes one or more processors, and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: displaying an analysis screen of a livestream associated with a selling item on a display; and displaying, on the analysis screen, a first object indicating a sales activity on a livestreamer side and a second object indicating reactions on viewers side together along a same time axis.Type: ApplicationFiled: October 16, 2023Publication date: September 26, 2024Inventors: Hao-Jung LO, Chia-Yi YANG, Yu-Hsin CHIANG, Cheng-Chieh CHANG, Sheng-Yen WANG, Liang-Fang TSAI
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Publication number: 20240308200Abstract: A method for transferring an electronic component includes the steps of: providing a carrier, wherein a surface of the carrier is loaded with an electronic component; providing a substrate; allowing a side of the substrate to face an electronic component-loaded side of the carrier, and maintaining an appropriate distance between the carrier and the substrate; providing an energy source for projecting an energy beam; splitting the energy beam into at least two sub-beams; focusing the at least two sub-beams, such that projection paths of the sub-beams are not parallel to each other; adjusting a distance between the carrier and the energy source as needed; and irradiating appropriate points on the electronic component-free side of the carrier with the at least two sub-beams to allow the electronic component to be separated from the carrier and transferred to the substrate.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Applicant: SKIILEUX ELECTRICITY INC.Inventors: SHENG-HSIANG YU, SHANG-WEI TSAI, TE-FU CHANG, CHENG-CHIEH CHANG
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Publication number: 20240312901Abstract: An interconnect structure including a contact via in an interlayer dielectric, a first conductive feature in a first dielectric layer, the first dielectric layer over the interlayer dielectric, a first liner in the first dielectric layer, the first liner comprising a first part in contact with a sidewall surface of the first conductive feature, and a second part in contact with a bottom surface of the first conductive feature. The interconnect structure includes a first cap layer in contact with a top surface of the first conductive feature, a second conductive feature in a second dielectric layer, the second dielectric layer over the first dielectric layer, a second liner in the second dielectric layer, wherein the first and second conductive features comprise a first conductive material, and the contact via, first liner, first cap layer, and second liner comprise a second conductive material chemically different than the first conductive material.Type: ApplicationFiled: July 12, 2023Publication date: September 19, 2024Inventors: Chien CHANG, Yen-Chun LIN, Jen-Wei LIU, Chih-Han TSENG, Harry CHIEN, Cheng-Hui WENG, Chun-Chieh LIN, Hung-Wen SU, Ming-Hsing TSAI, Chih-Wei CHANG
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Publication number: 20240298440Abstract: A memory device includes a substrate and a plurality of word lines. The word lines are disposed on the substrate. The word lines extend in the first direction and are arranged in the second direction. The first direction intersects the second direction. The memory device further includes a first sub-select gate extending in the first direction and separated from the outermost word line in the second direction. One end of the first sub-select gate has a first width in the second direction. The major portion of the first sub-select gate has a second width in the second direction. The second width is greater than the first width.Type: ApplicationFiled: January 11, 2024Publication date: September 5, 2024Inventors: Wen-Chieh TSAI, Cheng-Ta YANG
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Patent number: 12080594Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.Type: GrantFiled: July 25, 2022Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Lun Tsai, Huei-Wen Hsieh, Chun-Sheng Chen, Kai-Shiang Kuo, Jen-Wei Liu, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
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Publication number: 20240274590Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.Type: ApplicationFiled: April 29, 2024Publication date: August 15, 2024Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
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Patent number: 12061423Abstract: Microwave heating of debris collecting vanes within the source vessel of a lithography apparatus is used to accomplish uniform temperature distribution in order to reduce fall-on contamination and formation of clogs on the inner and outer surfaces of the vanes.Type: GrantFiled: September 28, 2021Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng Hung Tsai, Sheng-Kang Yu, Shang-Chieh Chien, Heng-Hsin Liu, Li-Jui Chen
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Publication number: 20240266335Abstract: An electronic package and the manufacturing method thereof are provided, in which a first electronic element and a second electronic element are disposed on a carrier structure, and the first electronic element and the second electronic element are electrically connected to each other by a wire. Therefore, by replacing some layers of the circuit layer of the carrier structure with the wire, the carrier structure can satisfy the functional signal transmission of the first and second electronic elements without configuring too many circuit layers, so as to shorten the process steps and time of the carrier structure, thereby effectively reducing the manufacturing cost of the electronic package.Type: ApplicationFiled: May 2, 2023Publication date: August 8, 2024Inventors: Huan-Shiang LI, Yih-Jenn JIANG, Cheng-Kai CHANG, Wei-Son TSAI, Yi-Chieh WANG