Patents by Inventor Cheng-Chieh Tu

Cheng-Chieh Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222196
    Abstract: Disclosed is a method of forming gate structures for n-type and p-type transistors. The method includes: forming an interfacial layer and high-K (HK) dielectric layer for the gate structures; forming an n-type metal layer over the HK dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the HK dielectric layer by fluorine passivation; patterning photo resist (PR) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned PR material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.
    Type: Application
    Filed: February 3, 2023
    Publication date: July 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tefu Yeh, Cheng-Chieh Tu, Hao-Hsin Chen, Jo-Chun Hung, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230420265
    Abstract: Disclosed is a method comprising: providing at least two structures with a metal layer over each; forming a patterned photolithographic layer over the metal layer over the first structure; removing the metal layer from the second structure via wet etch operations using a chemical etchant that is resistant to penetration into the photolithographic layer; and achieving, after wet etch operations, a remaining metal ratio of a distance X over a distance Y that is less than 179 and greater than 1, wherein X is the distance from a first line extending from an edge of the metal layer over the first structure to a second line extending from an edge of a channel region in the second structure, and Y is a second distance from the first line to a third line extending from an edge of the metal layer formed over the channel region in the first structure.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tefu Yeh, Cheng-Chieh Tu, Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230387233
    Abstract: In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 30, 2023
    Inventors: Yung-Hsiang CHAN, An-Hung TAI, Hui-Chi CHEN, J.F. CHUEH, Yen-Ta LIN, Ming-Chi HUANG, Cheng-Chieh TU, Jian-Hao CHEN, Kuo-Feng YU