Abstract: A semiconductor structure includes a first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die; and a molding material encapsulating the first die, the first conductive vias, the second conductive vias and the third conductive vias. A first width of each of the plurality of first conductive vias, a second width of each of the plurality of second conductive vias and a third width of the plurality of third conductive vias are different from each other.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.

Abstract: A method includes forming a reconstructed wafer, which includes placing a plurality of package components over a carrier, forming an interconnect structure over and electrically interconnecting the plurality of package components, forming top electrical connectors over and electrically connecting to the interconnect structure, and forming alignment marks at a same level as the top electrical connectors. Probe pads in the top electrical connectors are probed, and the probing is performed using the alignment marks for aligning to the probe pads. An additional package component is bonded to the reconstructed wafer through solder regions. The solder regions are physically joined to the top electrical connectors.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.

Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.

Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.

Abstract: A machining parameter automatic generation system includes a geometric data capturing module, a feature recognition learning network and a machining parameter learning network. The geometric data capturing module captures a geometric shape of a workpiece to generate a candidate feature list. The feature recognition learning network trains the candidate feature list according to a first neural network model to obtain an applicable feature list. The machining parameter learning network trains the applicable feature list and the candidate machining parameter according to a second neural network model to obtain an applicable machining parameter. The applicable machining parameter is used to generate a machining program, and the machining program is read by a machine tool for processing.

Abstract: A machining parameter automatic generation system includes a geometric data capturing module, a feature recognition learning network and a machining parameter learning network. The geometric data capturing module captures a geometric shape of a workpiece to generate a candidate feature list. The feature recognition learning network trains the candidate feature list according to a first neural network model to obtain an applicable feature list. The machining parameter learning network trains the applicable feature list and the candidate machining parameter according to a second neural network model to obtain an applicable machining parameter. The applicable machining parameter is used to generate a machining program, and the machining program is read by a machine tool for processing.

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract: A color calibrator of a display apparatus is disclosed. The color calibrator includes a color estimator for receiving a plurality of digital counts of initial colors of an image signal. The color estimator includes a first operator, a gray value electrical-optical converter, a mixed-color electrical-optical converter, an initial color electrical-optical converter, a plurality of linear transformers and a weighting operator. The gray value electrical-optical converter, the mixed-color electrical-optical converter and the initial color electrical-optical converter convert a gray value digital count, a mixed color digital count and an initial color digital count for generating a plurality conversion outputs according to a plurality of gray conversion curves, a plurality of mixed color conversion curves and a plurality of initial color converting curve. The weighting operator receives the conversion outputs and a plurality of weighting values to generate an analysis output signal.

Abstract: A color calibrator of a display apparatus is disclosed. The color calibrator includes a color estimator for receiving a plurality of digital counts of initial colors of an image signal. The color estimator includes a first operator, a gray value electrical-optical converter, a mixed-color electrical-optical converter, an initial color electrical-optical converter, a plurality of linear transformers and a weighting operator. The gray value electrical-optical converter, the mixed-color electrical-optical converter and the initial color electrical-optical converter convert a gray value digital count, a mixed color digital count and an initial color digital count for generating a plurality conversion outputs according to a plurality of gray conversion curves, a plurality of mixed color conversion curves and a plurality of initial color converting curve. The weighting operator receives the conversion outputs and a plurality of weighting values to generate an analysis output signal.

Abstract: A color correction method for liquid crystal displays (LCDs) is provided to eliminate crosstalk among color channels of the LCDs in the present invention. The color correction method includes steps of utilizing a channel-dependent Gain-Offset-Gamma (GOG) model to characterize a non-linear Electro-Optical Transfer Function (EOTF) of the LCDs in which crosstalk among color channels exists, converting the non-linear EOTF into a device-independent linear EOTF and modifying the linear EOTF to a target EOTF, so as to make the LCDs have expected colorimetry.

Abstract: A wireless audio system includes a host, a transmitter, and a receiver. The host includes a controller for controlling operations of the host, application software executed by the controller for producing audio signals, and a first electrical connector for connecting to a second electrical connector of the transmitter. The transmitter includes a first transceiver for wirelessly transmitting audio signals received from the host and for wirelessly transmitting and receiving data. The receiver includes a second transceiver for receiving audio signals wirelessly transmitted from the first transceiver of the transmitter, an audio output device for outputting the received audio signals, and a user interface for receiving a command from a user for controlling the host. The command is wirelessly transmitted from the receiver to the transmitter and delivered to the host, and the application software performs an action according to the command.