Abstract: An air guide module includes a casing and a first flexible air guide structure. The casing includes a first fixing portion. The first flexible air guide structure includes a first flexible cover and a second fixing portion connected to the first flexible cover. The first flexible air guide structure is fixed to the first fixing portion of the casing through the second fixing portion. The first flexible cover and a part of the casing form a heat dissipation channel. The first flexible cover is deflected relative to the casing when an airflow passes through the heat dissipation channel.

Abstract: A plug fixing structure is applied to fixing a power plug inserted into a power socket of an electronic device. The power plug has a plug portion and a main body portion. A first engaging structure is formed on an outer periphery of the power socket. The plug fixing structure includes a sleeve casing jacketing the main body portion to expose the plug portion and a first resilient arm having a first arm portion and a first front hook. The first arm portion protrudes from an outer surface of the sleeve casing. The first front hook extends from the first arm portion toward the first engaging structure. The first front hook is engaged with the first engaging structure when the plug portion is inserted into the power socket along a first axis, so as to constrain movement of the power plug along the first axis relative to the power socket.

Abstract: A plug fixing structure is applied to fixing a power plug inserted into a power socket of an electronic device. The power plug has a plug portion and a main body portion. A first engaging structure is formed on an outer periphery of the power socket. The plug fixing structure includes a sleeve casing jacketing the main body portion to expose the plug portion and a first resilient arm having a first arm portion and a first front hook. The first arm portion protrudes from an outer surface of the sleeve casing. The first front hook extends from the first arm portion toward the first engaging structure. The first front hook is engaged with the first engaging structure when the plug portion is inserted into the power socket along a first axis, so as to constrain movement of the power plug along the first axis relative to the power socket.

Abstract: An electronic device includes a socket and a casing. The socket includes a first connecting structure and a second connecting structure. The casing includes a first side wall and a second side wall, wherein the first side wall is essentially perpendicular to the second side wall. The first side wall includes a third connecting structure and the second side wall includes a fourth connecting structure. The first connecting structure is connected to the third connecting structure along a first connecting axis and the second connecting structure is connected to the fourth connecting structure along a second connecting axis, such that the socket is fixed on the casing, wherein the first connecting axis is essentially perpendicular to the second connecting axis.

Abstract: A speaker module includes a bracket, a plurality of first cushion members, a speaker and a plurality of second cushion members. The bracket includes a plurality of first pillars. Each of the first cushion members is disposed on one of the first pillars. The speaker is connected to the first cushion members. The second cushion members are connected to a periphery of the bracket.

Abstract: A speaker module includes a bracket, a plurality of first cushion members, a speaker and a plurality of second cushion members. The bracket includes a plurality of first pillars. Each of the first cushion members is disposed on one of the first pillars. The speaker is connected to the first cushion members. The second cushion members are connected to a periphery of the bracket.

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.

Abstract: A method of manufacturing a memory device. The memory device comprises a trench in a substrate, a capacitor at the low portion of the trench, a collar dielectric layer overlying the capacitor and covering a portion of the sidewall of the trench, and a conductive layer filling a portion of the trench over the capacitor. First, a first mask layer is formed on the conductive layer, wherein a bottom portion of the first mask layer is thicker than the side portion thereof in the trench. A second mask layer is formed on the first mask layer. Next, a portion of the second mask layer in the trench is ion implanted. The unimplanted portion of the second mask layer is removed.

Abstract: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.

Abstract: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.

Abstract: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

Abstract: A method of manufacturing a memory device. The memory device comprises a trench in a substrate, a capacitor at the low portion of the trench, a collar dielectric layer overlying the capacitor and covering a portion of the sidewall of the trench, and a conductive layer filling a portion of the trench over the capacitor. First, a first mask layer is formed on the conductive layer, wherein a bottom portion of the first mask layer is thicker than the side portion thereof in the trench. A second mask layer is formed on the first mask layer. Next, a portion of the second mask layer in the trench is ion implanted. The unimplanted portion of the second mask layer is removed.

Abstract: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated from the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

Abstract: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

Abstract: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned.

Abstract: A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.

Abstract: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.