Patents by Inventor Cheng-Ching Lee

Cheng-Ching Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979980
    Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: May 7, 2024
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Publication number: 20240136221
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11937370
    Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 19, 2024
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Patent number: 11935783
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11916131
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Patent number: 8111206
    Abstract: The invention discloses a high electromagnetic transmission composite structure for reducing the transmission loss of an electromagnetic wave. The high electromagnetic transmission composite structure includes a first composite structure layer, a second composite structure layer, and a first buffer layer. The first composite structure layer has a first thickness and a first dielectric constant. The second composite structure layer has a second thickness and a second dielectric constant. The first buffer is disposed between the first composite structure layer and the second composite structure layer and has a third thickness and a third dielectric constant. The transmission loss of the electromagnetism wave can be adjusted by adjusting the first thickness, the first dielectric constant, the second thickness, the second dielectric constant, the third thickness, and the third dielectric constant.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 7, 2012
    Assignee: Chung-Shan Institute of Science and Technology, Armaments Bureau, Ministry of National Defense
    Inventors: Cheng-Ching Lee, Jiunn-Shyong Lin, Shin-Hon Chen, Yie-Fan King, Dar-Chuen Lin
  • Publication number: 20110050370
    Abstract: The invention discloses a high electromagnetic transmission composite structure for reducing the transmission loss of an electromagnetic wave. The high electromagnetic transmission composite structure includes a first composite structure layer, a second composite structure layer, and a first buffer layer. The first composite structure layer has a first thickness and a first dielectric constant. The second composite structure layer has a second thickness and a second dielectric constant. The first buffer is disposed between the first composite structure layer and the second composite structure layer and has a third thickness and a third dielectric constant. The transmission loss of the electromagnetism wave can be adjusted by adjusting the first thickness, the first dielectric constant, the second thickness, the second dielectric constant, the third thickness, and the third dielectric constant.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventors: Cheng-Ching Lee, Jiunn-Shyong Lin, Shin-Hon Chen, Yie-Fan King, Dar-Chuen Lin
  • Patent number: 6298185
    Abstract: A distributed fiber-grating-based sensing system, the system comprises one or more scanned birefringence fiber interferometers to detect the small wavelength shift of the light reflected from the fiber grating, a wavelength demultiplexer to separate the lights from each fiber grating, a reference fiber grating for determining the absolute optical wavelengths. Compared with the prior art, the system has advantages of easier fabrication, better stabilization, and can be customized for different applications.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: October 2, 2001
    Assignee: Chung-Shan Institute of Science and Technology
    Inventors: Yinchieh Lai, Yuh-Wen Chen, Ching-Long Ong, Ben Hong, Jiam-Hwa Lee, Rwei-Ping Ma, Shih-Chu Wu, Ming-Yang Tsai, Cheng-Ching Lee