Patents by Inventor Cheng Choi Yong
Cheng Choi Yong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9337167Abstract: A method of attaching bond wires to bond pads on an active surface of a semiconductor die, where the bond pads are disposed along four side edges of the die, and have aluminum top layers. The method includes attaching first bond wires to first bond pads on first and second opposing sides of the die using a first group of settings and attaching second bond wires to the bond pads on third and fourth sides of the die that oppose each other and are adjacent the first and second sides, using a second group of settings. The first and second groups of settings include first and second scrub settings that are different from each other. Employing two separate scrub settings allows for reduced splashing of the aluminum cap layer on the die pad from splashing onto passivation edges of the bond pads.Type: GrantFiled: November 24, 2014Date of Patent: May 10, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Boh Kid Wong, Cheng Choi Yong
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Publication number: 20150279810Abstract: A method of attaching bond wires to bond pads on an active surface of a semiconductor die, where the bond pads are disposed along four side edges of the die, and have aluminum top layers. The method includes attaching first bond wires to first bond pads on first and second opposing sides of the die using a first group of settings and attaching second bond wires to the bond pads on third and fourth sides of the die that oppose each other and are adjacent the first and second sides, using a second group of settings. The first and second groups of settings include first and second scrub settings that are different from each other. Employing two separate scrub settings allows for reduced splashing of the aluminum cap layer on the die pad from splashing onto passivation edges of the bond pads.Type: ApplicationFiled: November 24, 2014Publication date: October 1, 2015Inventors: Boh Kid Wong, Cheng Choi Yong
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Publication number: 20150235981Abstract: A method of attaching a bond wire to an electrical contact pad includes performing a first electric flame off (EFO) on the end of the bond wire at a first setting to pre-form a free air ball (FAB) on the end of the wire, and performing a second EFO on the end of the bond wire at a second setting, after performing the first EFO, to fully form the FAB.Type: ApplicationFiled: November 24, 2014Publication date: August 20, 2015Inventors: Poh Leng Eu, Cheng Choi Yong
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Patent number: 7626276Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.Type: GrantFiled: May 17, 2007Date of Patent: December 1, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Susan H. Downey, James W. Miller, Cheng Choi Yong
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Publication number: 20080182120Abstract: A bond pad (12, 14) for a semiconductor device (10) is generally L-shaped and includes a first portion (20, 24) for receiving a bond wire, and a second portion (22, 26) extending substantially perpendicularly from the first portion (20, 24). The bond pad (12) may include a third portion (16, 18) adjacent to the first portion (20). The third portion (16, 18) may be an embedded power pad (16) or an embedded ground pad (18).Type: ApplicationFiled: January 28, 2007Publication date: July 31, 2008Inventors: Lan Chu Tan, Heng Keong Yip, Cheng Choi Yong
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Patent number: 7241636Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.Type: GrantFiled: January 11, 2005Date of Patent: July 10, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Susan H. Downey, James W. Miller, Cheng Choi Yong
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Publication number: 20070026573Abstract: A method of making a stacked die package (50) includes attaching and electrically connecting a first integrated circuit (IC) die (52) to a base carrier (56). A plurality of successive layers (54A, 54B and 54C) of an adhesive material (54) is formed on the first die (52). A second die (72) is attached to the first die (52) with the adhesive material (54) such that the successive layers of adhesive material (54A, 54B and 54C) maintain a predetermined spacing (H) between the first die (52) and the second die (72). The second die (72) is electrically connected to the base carrier (56).Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: Aminuddin Ismail, Wai Yew Lo, Kong Bee Tiu, Cheng Choi Yong
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Patent number: 7160755Abstract: A method of forming a substrateless semiconductor package (10) includes forming a carrier (16) on a base plate (12) and attaching an integrated circuit (IC) die (32) to the carrier (16). The IC die (32) then is electrically connected to the carrier (16). A molding operation is performed to encapsulate the IC die (32), the electrical connections (36) and the carrier (16). Thereafter, the base plate (12) is removed.Type: GrantFiled: April 18, 2005Date of Patent: January 9, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Cheng Choi Yong, Kong Bee Tiu
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Patent number: 6933614Abstract: An integrated circuit die (10) has a copper contact (16, 18), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which reacts with the native copper oxide to form an organic coating (12, 14) on the copper contact in order to prevent further copper oxidation. In this manner, further processing at higher temperatures, such as those greater than 100 degrees Celsius, is not inhibited by excessive copper oxidation. For example, due to the organic coating, the high temperature of the wire bond process does not result in excessive oxidation which would prevent reliable wire bonding. Thus, the formation of the organic coating allows for a reliable and thermal resistance wire bond (32, 34). Alternatively, the organic coating can be formed over exposed copper at any time during the formation of the integrated circuit die to prevent or limit the formation of copper oxidation.Type: GrantFiled: September 15, 2003Date of Patent: August 23, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Chu-Chung Lee, Fuaida Harun, Kevin J. Hess, Lan Chu Tan, Cheng Choi Yong
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Publication number: 20040195696Abstract: An integrated circuit die (10) has a copper contact (16, 18), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which reacts with the native copper oxide to form an organic coating (12, 14) on the copper contact in order to prevent further copper oxidation. In this manner, further processing at higher temperatures, such as those greater than 100 degrees Celsius, is not inhibited by excessive copper oxidation. For example, due to the organic coating, the high temperature of the wire bond process does not result in excessive oxidation which would prevent reliable wire bonding. Thus, the formation of the organic coating allows for a reliable and thermal resistance wire bond (32, 34). Alternatively, the organic coating can be formed over exposed copper at any time during the formation of the integrated circuit die to prevent or limit the formation of copper oxidation.Type: ApplicationFiled: September 15, 2003Publication date: October 7, 2004Inventors: Chu-Chung Lee, Fuaida Harun, Kevin J. Hess, Lan Chu Tan, Cheng Choi Yong
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Publication number: 20030230796Abstract: An electrical connection for connecting multiple bonding pads of different devices. The electrical connection includes a first bonding pad on a first device and a bump disposed on the first bonding pad. A first wire is stitch bonded to the bump on the first device and electrically connected to a bonding pad of a second device. A second wire is ball bonded to the stitch bond of the first wire. The second wire is also electrically connected to a bonding pad of a third device. Thus, the second and third devices are connected to a single bonding pad of the first device. The size of the bonding pad is not unnecessarily increased to accommodate multiple wire bonds. Further, additional wires may be stitch bonded between the first stitch bond and the ball bond.Type: ApplicationFiled: June 12, 2002Publication date: December 18, 2003Inventors: Aminuddin Ismail, Lan Chu Tan, Kong Bee Tiu, Cheng Choi Yong
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Publication number: 20030111720Abstract: An integrated circuit die (106) of a stacked multichip package (100) has a body (122) with a bottom surface (124) for being adhered to a surface of another integrated circuit die (104) of the stacked multichip package (100), and a top surface (126). The top surface (126) includes bonding pads (128). The body (122) also includes steps (130) extending along a periphery of the bottom surface (124) such that an area of the bottom surface (124) is less than an area of the top surface (126) and such that the die (106) has a T-shaped cross-section. When the die (106) is attached on top of another die (104), the steps (130) form a space for the wirebonds of the wires connecting the other die (104) to a carrier (102).Type: ApplicationFiled: December 18, 2001Publication date: June 19, 2003Inventors: Lan Chu Tan, Cheng Choi Yong, Chee Seng Foong, Ruzaini Bin Ibrahim