Abstract: A method for preparing a long-chain branched polypropylene includes subjecting a T-reagent to a polymerization reaction with propylene in the presence of a catalyst composition. The catalyst composition includes an alkylaluminoxane and a metallocene-based catalyst. The metallocene-based catalyst contains a metal selected from the group consisting of titanium (Ti), zirconium (Zr), and hafnium (Hf). The T-reagent having an alkenyl silyl functional group is selected from the group consisting of 1,2-bis[dimethyl(vinyl)silyl]ethane, dimethyldivinylsilane, 7-octenyldimethyl(vinyl)silane, 7-octenyldimethyl(allyl)silane, 4-(but-3-enyl)phenyldimethyl(vinyl)silane, 4-(but-3-enyl)phenyldimethyl(allyl)silane, and combinations thereof.

Abstract: This disclosure provides systems, methods, and devices for wireless communication that support transmission of power limit indications for a UE associated with different frequency bands. In a first aspect, a method of wireless communication includes detecting a first trigger condition for transmission of at least a first indication of a first transmission power limit of the UE and a second indication of a second transmission power limit of the UE, wherein the first transmission power limit is associated with a first frequency band supported by the UE and the second transmission power limit is associated with a second frequency band supported by the UE and transmitting, to a first network node associated with the first frequency band, the first indication and the second indication in accordance with detection of the first trigger condition. Other aspects and features are also claimed and described.

Abstract: A PCI-E bus standard compliant multifunctional interface board includes a substrate, a PCI-E connector, a storage device, a non-storage device and a signal dispatch device. The PCI-E connector is provided on the substrate and is configured to be electrically connected to a host. The storage device and the non-storage device are provided on the substrate. The signal dispatch device is provided on the substrate and includes: an upstream port, a downstream port and an I/O controller. The upstream port is electrically connected to the PCI-E connector. The downstream port is electrically connected to the storage device and/or the non-storage device. The I/O controller is electrically connected to the upstream port and the downstream port to control an electrical connection relationship between the host and the storage device and/or the non-storage device.

Abstract: A wearable device and a method for selecting and interpreting light intensity data values applicable thereto. The wearable device includes a light emitting unit and a spectrum sensing unit. The method includes steps of: controlling the light-emitting unit to simultaneously emit a mixed light including multiple spectrum frequency bands to enter inside skin of the user; controlling the spectrum sensing unit to sense the intensity of an outgoing light from inside skin of the user at a series of sampling time to generate a spectrum data set including a plurality of groups of frequency band-light intensity data values; and selecting at least one of a first group of frequency band-light intensity data values satisfying a signal quality index in the spectrum data set to perform a data interpretation at a first judgment time point.

Abstract: An eye image capturing and processing device is provided. The device includes a portable user terminal body and an application program installed in the portable user terminal body. The portable user terminal body has thereon an image capturing module for capturing an eye image of a user to generate instant image data. The application program receives the instant image data and performs a data processing procedure, and takes an automatic selfie or generates an indication signal to instruct the user to take a manual selfie when a preset condition is satisfied, thereby generating a to-be-diagnosed image corresponding to the eye of the user.

Abstract: A PCI-E bus standard compliant multifunctional interface board includes a substrate, a PCI-E connector, a storage device, a non-storage device and a signal dispatch device. The PCI-E connector is provided on the substrate and is configured to be electrically connected to a host. The storage device and the non-storage device are provided on the substrate. The signal dispatch device is provided on the substrate and includes: an upstream port, a downstream port and an I/O controller. The upstream port is electrically connected to the PCI-E connector. The downstream port is electrically connected to the storage device and/or the non-storage device. The I/O controller is electrically connected to the upstream port and the downstream port to control an electrical connection relationship between the host and the storage device and/or the non-storage device.

Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. The phase change layer includes a GeSbTe material that contains a Ge content of about 20 at % or less, a Sb content of about 30 at % or more, and a Te content of about 40 at % at or more.

Abstract: A memory cell includes a bottom electrode, a thermal preservation layer, a first dielectric layer, a variable resistance layer, and a top electrode. The bottom electrode includes a first electrode and a second electrode spatially separated from the first electrode. The thermal preservation layer is partially sandwiched between the first electrode and the second electrode. The first dielectric layer laterally surrounds the bottom electrode and the thermal preservation layer. The variable resistance layer is disposed on the second electrode, the thermal preservation layer, and the first dielectric layer. The top electrode is disposed on the variable resistance layer.

Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

Abstract: Semiconductor devices and methods of manufacturing are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

Abstract: A charging device indicating battery percentage, including a power source connector for connecting with a power supply terminal, a charging connector for connecting with a handheld device, a cable connected between the power source connector and the charging connector, a control unit and a display unit, where the control unit is programmed to read a battery percentage of the handheld device from a memory of the handheld device through a signal path of the cable, and drive the display unit to display the battery percentage.

Abstract: A cable assembly capable of detecting bidirectional charging-current, including a first interface, a second interface, and a cable electrically connected between the first interface and the second interface, the cable including a series resistor network, which has a first node, a common node, a second node, a first resistor and a second resistor, the first node being coupled to the first interface, the common node being coupled to a ground, the second node being coupled to the second interface, the first resistor being coupled between the first node and the common node, and the second resistor being coupled between the common node and the second node, whereby the first node and the second node can provide two single-end voltages or two differential voltages to represent a forward charging current and a reverse charging current respectively.

Abstract: A chip-scale integrated multi-wavelength biological sensing device employing a plurality of filter-sensor assemblies is provided. The plurality of filter-sensor assemblies can include sufficient number of optical channels enabled by plasmonic filters having different nanoscale patterns and provided directly on an array of photodetectors. Combined with simultaneous illumination of light including multiple peak wavelengths with small full width at half maximum values, the independent optical channels of the plurality of filter-sensor assemblies enable correlation of detected optical signals with biological parameters. Signal processing methods for robustly extracting The PPG signals can be extracted by a robust signal processing method. Successful measurement of peripheral blood oxygen (SpO2) and blood pressure has been demonstrated.

Abstract: The present invention provides an expandable interface board. The interface board is an interface board conforming to M.2 interface protocol specification, comprises a plurality of data storage elements, a data transmission interface, a controller, and at least one connection seat. The data transmission interface comprises a plurality of first interface pins and a plurality of second interface pins. The interface board is electrically connected to an external electronic device via the connection seat. Wherein the first interface pins are defined for transmitting data signals of the data storage elements, and the second interface pins are defined for transmitting data signals of the external electronic device. Accordingly, an electronic product applied by the interface board is able to expand it's functions by the external electronic device connected to the connection seat of the interface board.