Patents by Inventor Cheng Chun Chang

Cheng Chun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12349607
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Patent number: 12342548
    Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Cheng-Hsien Wu, Cheng-Chun Chang, Elia Ambrosi, Hengyuan Lee, Ying-Yu Chen, Xinyu Bao, Tung-Ying Lee
  • Patent number: 12174768
    Abstract: A PCI-E bus standard compliant multifunctional interface board includes a substrate, a PCI-E connector, a storage device, a non-storage device and a signal dispatch device. The PCI-E connector is provided on the substrate and is configured to be electrically connected to a host. The storage device and the non-storage device are provided on the substrate. The signal dispatch device is provided on the substrate and includes: an upstream port, a downstream port and an I/O controller. The upstream port is electrically connected to the PCI-E connector. The downstream port is electrically connected to the storage device and/or the non-storage device. The I/O controller is electrically connected to the upstream port and the downstream port to control an electrical connection relationship between the host and the storage device and/or the non-storage device.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: December 24, 2024
    Assignee: INNODISK CORPORATION
    Inventors: Hsi-Hsi Wu, Cheng-Chun Chang
  • Publication number: 20240215875
    Abstract: A wearable device and a method for selecting and interpreting light intensity data values applicable thereto. The wearable device includes a light emitting unit and a spectrum sensing unit. The method includes steps of: controlling the light-emitting unit to simultaneously emit a mixed light including multiple spectrum frequency bands to enter inside skin of the user; controlling the spectrum sensing unit to sense the intensity of an outgoing light from inside skin of the user at a series of sampling time to generate a spectrum data set including a plurality of groups of frequency band-light intensity data values; and selecting at least one of a first group of frequency band-light intensity data values satisfying a signal quality index in the spectrum data set to perform a data interpretation at a first judgment time point.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 4, 2024
    Inventors: CHENG-CHUN CHANG, PO-WEN LU
  • Publication number: 20240221155
    Abstract: An eye image capturing and processing device is provided. The device includes a portable user terminal body and an application program installed in the portable user terminal body. The portable user terminal body has thereon an image capturing module for capturing an eye image of a user to generate instant image data. The application program receives the instant image data and performs a data processing procedure, and takes an automatic selfie or generates an indication signal to instruct the user to take a manual selfie when a preset condition is satisfied, thereby generating a to-be-diagnosed image corresponding to the eye of the user.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 4, 2024
    Inventors: CHENG-CHUN CHANG, Po-Wen Lu
  • Publication number: 20240168902
    Abstract: A PCI-E bus standard compliant multifunctional interface board includes a substrate, a PCI-E connector, a storage device, a non-storage device and a signal dispatch device. The PCI-E connector is provided on the substrate and is configured to be electrically connected to a host. The storage device and the non-storage device are provided on the substrate. The signal dispatch device is provided on the substrate and includes: an upstream port, a downstream port and an I/O controller. The upstream port is electrically connected to the PCI-E connector. The downstream port is electrically connected to the storage device and/or the non-storage device. The I/O controller is electrically connected to the upstream port and the downstream port to control an electrical connection relationship between the host and the storage device and/or the non-storage device.
    Type: Application
    Filed: April 5, 2023
    Publication date: May 23, 2024
    Inventors: Hsi-Hsi Wu, Cheng-Chun Chang
  • Publication number: 20240074337
    Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. The phase change layer includes a GeSbTe material that contains a Ge content of about 20 at % or less, a Sb content of about 30 at % or more, and a Te content of about 40 at % at or more.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hengyuan Lee, Cheng-Chun Chang, Chen-Feng Hsu, Tung-Ying Lee, Xinyu BAO
  • Publication number: 20240016072
    Abstract: A memory cell includes a bottom electrode, a thermal preservation layer, a first dielectric layer, a variable resistance layer, and a top electrode. The bottom electrode includes a first electrode and a second electrode spatially separated from the first electrode. The thermal preservation layer is partially sandwiched between the first electrode and the second electrode. The first dielectric layer laterally surrounds the bottom electrode and the thermal preservation layer. The variable resistance layer is disposed on the second electrode, the thermal preservation layer, and the first dielectric layer. The top electrode is disposed on the variable resistance layer.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hengyuan Lee, Yu-Sheng Chen, Cheng-Chun Chang, Xinyu BAO
  • Patent number: 11856876
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Publication number: 20230389452
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Publication number: 20220415968
    Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.
    Type: Application
    Filed: February 10, 2022
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Cheng-Hsien Wu, Cheng-Chun Chang, Elia Ambrosi, Hengyuan Lee, Ying-Yu Chen, Xinyu BAO, Tung-Ying Lee
  • Publication number: 20220311254
    Abstract: A charging device indicating battery percentage, including a power source connector for connecting with a power supply terminal, a charging connector for connecting with a handheld device, a cable connected between the power source connector and the charging connector, a control unit and a display unit, where the control unit is programmed to read a battery percentage of the handheld device from a memory of the handheld device through a signal path of the cable, and drive the display unit to display the battery percentage.
    Type: Application
    Filed: December 1, 2021
    Publication date: September 29, 2022
    Inventor: Cheng-Chun CHANG
  • Publication number: 20220310914
    Abstract: Semiconductor devices and methods of manufacturing are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 29, 2022
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Publication number: 20220200304
    Abstract: A cable assembly capable of detecting bidirectional charging-current, including a first interface, a second interface, and a cable electrically connected between the first interface and the second interface, the cable including a series resistor network, which has a first node, a common node, a second node, a first resistor and a second resistor, the first node being coupled to the first interface, the common node being coupled to a ground, the second node being coupled to the second interface, the first resistor being coupled between the first node and the common node, and the second resistor being coupled between the common node and the second node, whereby the first node and the second node can provide two single-end voltages or two differential voltages to represent a forward charging current and a reverse charging current respectively.
    Type: Application
    Filed: June 29, 2021
    Publication date: June 23, 2022
    Inventor: Cheng-Chun CHANG
  • Publication number: 20210059585
    Abstract: A chip-scale integrated multi-wavelength biological sensing device employing a plurality of filter-sensor assemblies is provided. The plurality of filter-sensor assemblies can include sufficient number of optical channels enabled by plasmonic filters having different nanoscale patterns and provided directly on an array of photodetectors. Combined with simultaneous illumination of light including multiple peak wavelengths with small full width at half maximum values, the independent optical channels of the plurality of filter-sensor assemblies enable correlation of detected optical signals with biological parameters. Signal processing methods for robustly extracting The PPG signals can be extracted by a robust signal processing method. Successful measurement of peripheral blood oxygen (SpO2) and blood pressure has been demonstrated.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 4, 2021
    Inventors: Byung IL CHOI, Cheng-Chun CHANG, Chien-Ta WU
  • Patent number: 10437767
    Abstract: The present invention provides an expandable interface board. The interface board is an interface board conforming to M.2 interface protocol specification, comprises a plurality of data storage elements, a data transmission interface, a controller, and at least one connection seat. The data transmission interface comprises a plurality of first interface pins and a plurality of second interface pins. The interface board is electrically connected to an external electronic device via the connection seat. Wherein the first interface pins are defined for transmitting data signals of the data storage elements, and the second interface pins are defined for transmitting data signals of the external electronic device. Accordingly, an electronic product applied by the interface board is able to expand it's functions by the external electronic device connected to the connection seat of the interface board.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 8, 2019
    Assignee: INNODISK CORPORATION
    Inventors: Che-Ming Hsu, Cheng-Chun Chang
  • Patent number: 10157781
    Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a conductive material in the trench and over a top surface of the material layer and polishing the conductive material with a slurry to expose the top surface of the material layer and to form a conductive structure in the trench. The method for forming a semiconductor structure further includes forming a material layer over a substrate and forming a trench in the material layer. The method for forming a semiconductor structure further includes removing the slurry with a reducing solution. In addition, the reducing solution includes a reducing agent, and a standard electrode voltage of the conductive material is greater than a standard electrode voltage of the reducing agent.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Cheng-Chun Chang, Yi-Sheng Lin, Pinlei Edmund Chu, Liang-Guang Chen
  • Publication number: 20180356865
    Abstract: The presented invention provides a data storage device. The memory device comprises an interface card and an expansion board. The interface card comprises a controller, a transmission interface, a plurality of first data storage elements and a first connector. The expansion board comprises a plurality of second data storage elements and a second connector. The expansion board is connected to the first connector of the interface card by the second connector to be stacked on the interface card. The controller is able to access data of the first data storage elements and the second data storage elements. Thus, the data storage capacity of the data storage device can be expanded by the expansion board, having the data storage elements, configured on the interface card.
    Type: Application
    Filed: December 26, 2017
    Publication date: December 13, 2018
    Inventors: WEI-TING CHANG, CHENG-CHUN CHANG
  • Publication number: 20180329849
    Abstract: The present invention provides an expandable interface board. The interface board is an interface board conforming to M.2 interface protocol specification, comprises a plurality of data storage elements, a data transmission interface, a controller, and at least one connection seat. The data transmission interface comprises a plurality of first interface pins and a plurality of second interface pins. The interface board is electrically connected to an external electronic device via the connection seat. Wherein the first interface pins are defined for transmitting data signals of the data storage elements, and the second interface pins are defined for transmitting data signals of the external electronic device. Accordingly, an electronic product applied by the interface board is able to expand it's functions by the external electronic device connected to the connection seat of the interface board.
    Type: Application
    Filed: September 12, 2017
    Publication date: November 15, 2018
    Inventors: Che-Ming HSU, Cheng-Chun CHANG
  • Publication number: 20180166331
    Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a conductive material in the trench and over a top surface of the material layer and polishing the conductive material with a slurry to expose the top surface of the material layer and to form a conductive structure in the trench. The method for forming a semiconductor structure further includes forming a material layer over a substrate and forming a trench in the material layer. The method for forming a semiconductor structure further includes removing the slurry with a reducing solution. In addition, the reducing solution includes a reducing agent, and a standard electrode voltage of the conductive material is greater than a standard electrode voltage of the reducing agent.
    Type: Application
    Filed: January 9, 2017
    Publication date: June 14, 2018
    Inventors: Chun-Wei HSU, Chi-Jen LIU, Cheng-Chun CHANG, Yi-Sheng LIN, Pinlei Edmund CHU, Liang-Guang CHEN