Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: The disclosure provides a power allocation method for non-orthogonal multiple access (NOMA) systems and a base station thereof. The method includes the following steps: receiving a first channel estimation error parameter from first user equipment, and receiving a second channel estimation error parameter from second user equipment; configuring a first minimum rate requirement of the first user equipment and a second minimum rate requirement of the second user equipment; determining a power allocation factor according to the first channel estimation error parameter, the second channel estimation error parameter, the first minimum rate requirement, and the second minimum rate requirement; and determining first transmission power for the first user equipment and second transmission power for the second user equipment according to the power allocation factor.

Abstract: The disclosure provides a power allocation method for non-orthogonal multiple access (NOMA) systems and a base station thereof. The method includes the following steps: receiving a first channel estimation error parameter from first user equipment, and receiving a second channel estimation error parameter from second user equipment; configuring a first minimum rate requirement of the first user equipment and a second minimum rate requirement of the second user equipment; determining a power allocation factor according to the first channel estimation error parameter, the second channel estimation error parameter, the first minimum rate requirement, and the second minimum rate requirement; and determining first transmission power for the first user equipment and second transmission power for the second user equipment according to the power allocation factor.