Abstract: An example device is to monitor communications throughput rates and select modulation and coding protocols in order to minimize specific absorption rates experienced by users of the devices by minimizing or reducing transmission power settings.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A method, computer program product, and computer system for public speaking guidance is provided. A processor retrieves speaker data regarding a speech made by a user. A processor separates the speaker data into one or more speaker modalities. A processor extracts one or more speaker features from the speaker data for the one or more speaker modalities. A processor generates a performance classification based on the one or more speaker features. A processor sends to the user guidance regarding the speech based on the performance classification.

Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: The present disclosure provides intelligent radio frequency interference mitigation in a computing platform. The computing platform includes a processor, a memory, a system clock and a wireless network interface. The system clock can be controlled so that the processor and/or the memory may operate at a slow frequency or a fast frequency. The wireless network may operate on a radio channel that experiences radio frequency interference at the fast frequency. The system clock may be intelligently controlled to select the slow frequency to reduce radio frequency interference to prioritize execution of a network application, or to select the fast frequency to increase processor speed and prioritize execution of a local application.

Abstract: An electronic device includes a first main body, a first electrical connector, and an insert member. The first main body has an insertion end and one or more holes located at the insertion end. The first electrical connector is disposed at the insertion end. The insert member is coupled to the first main body through the one or more holes and includes a plurality of ribs and a plurality of removed portions. Each of the ribs extends away from the insertion end. The ribs and the removed portions are sequentially and linearly arranged according to a coding pattern.

Abstract: A waste collection apparatus for collecting waste in water is provided. The waste collection apparatus includes a floating device and a waste collection device coupled to the floating device. The waste collection device includes a fluid ejection element, and the flow out of the fluid ejection element flows toward a space where waste is collected.

Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: An electronic device includes a first main body, a first electrical connector, and an insert member. The first main body has an insertion end and one or more holes located at the insertion end. The first electrical connector is disposed at the insertion end. The insert member is coupled to the first main body through the one or more holes and includes a plurality of ribs and a plurality of removed portions. Each of the ribs extends away from the insertion end. The ribs and the removed portions are sequentially and linearly arranged according to a coding pattern.

Abstract: An electronic device includes a first main body, a first electrical connector, and an insert member. The first main body has an insertion end and one or more holes located at the insertion end. The first electrical connector is disposed at the insertion end. The insert member is coupled to the first main body through the one or more holes and includes a plurality of ribs and a plurality of removed portions. Each of the ribs extends away from the insertion end. The ribs and the removed portions are sequentially and linearly arranged according to a coding pattern.

Abstract: An electronic device includes a first main body, a first electrical connector, and an insert member. The first main body has an insertion end and one or more holes located at the insertion end. The first electrical connector is disposed at the insertion end. The insert member is coupled to the first main body through the one or more holes and includes a plurality of ribs and a plurality of removed portions. Each of the ribs extends away from the insertion end. The ribs and the removed portions are sequentially and linearly arranged according to a coding pattern.

Abstract: A power supply device is disclosed. A circuit board is disposed inside a conductive housing. A rectifying module is disposed on the circuit board and has primary and secondary sides. The grounding module includes a first grounding element, a second grounding element, and a fastening element. Two terminals of the first surge protection module are respectively electrically connected to the primary side and the first grounding element. Two terminals of the second surge protection module are respectively electrically connected to the secondary side and the second grounding element. The second grounding element and the first grounding element are not directly connected. The fastening element passes through the conductive housing, the circuit board, the first grounding element, and the second grounding element so that the conductive housing, the first grounding element, and the second grounding element are electrically connected to one another.

Abstract: A power supply device is disclosed. A circuit board is disposed inside a conductive housing. A rectifying module is disposed on the circuit board and has primary and secondary sides. The grounding module includes a first grounding element, a second grounding element, and a fastening element. Two terminals of the first surge protection module are respectively electrically connected to the primary side and the first grounding element. Two terminals of the second surge protection module are respectively electrically connected to the secondary side and the second grounding element. The second grounding element and the first grounding element are not directly connected. The fastening element passes through the conductive housing, the circuit board, the first grounding element, and the second grounding element so that the conductive housing, the first grounding element, and the second grounding element are electrically connected to one another.

Abstract: A cover structure for an outdoor casing includes a top cover and an inner cover-brow. A side wall is formed on the periphery of the top cover. The inner cover-brow has a first brow plate and a second brow plate. An inclined plate interconnects the first brow plate and the second brow plate. The inclined plate has a plurality of through holes. The second brow plate is connected to the side wall. The interior included angle of the first brow plate and the inclined plate is an acute angle. The cover structure not only helps the outdoor casing to ventilate and dissipate heat, but also enhances the outdoor casing's water repellency.

Abstract: A cover structure for an outdoor casing includes a top cover and an inner cover-brow. A side wall is formed on the periphery of the top cover. The inner cover-brow has a first brow plate and a second brow plate. An inclined plate interconnects the first brow plate and the second brow plate. The inclined plate has a plurality of through holes. The second brow plate is connected to the side wall. The interior included angle of the first brow plate and the inclined plate is an acute angle. The cover structure not only helps the outdoor casing to ventilate and dissipate heat, but also enhances the outdoor casing's water repellency.