Patents by Inventor Cheng-Chun Yeh

Cheng-Chun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10211813
    Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: February 19, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Cheng-Chun Yeh
  • Publication number: 20180287366
    Abstract: EMarker and associated cable and method. The cable includes a CC (configuration channel) wire, the eMarker includes an active trigger circuit and a protection circuit coupled to the active trigger circuit and the CC wire. When a second port connects a first port via the cable, if a predefined event happens, the active trigger circuit triggers the protection circuit to change an electric characteristic of the CC wire, such that the first port detects a detachment of the second port.
    Type: Application
    Filed: January 11, 2018
    Publication date: October 4, 2018
    Applicant: VIA Technologies, Inc.
    Inventors: Cheng-Chun YEH, Wei-Hang LIN, Yu-Lung LIN, Feng-Kuan SU
  • Publication number: 20170047908
    Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.
    Type: Application
    Filed: December 21, 2015
    Publication date: February 16, 2017
    Inventor: Cheng-Chun Yeh