Patents by Inventor Cheng-Chung Chou
Cheng-Chung Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250072164Abstract: A method for forming an indium gallium nitride quantum well structure is disclosed. The method includes forming a gallium nitride microdisk on a substrate, with the gallium nitride microdisk having an inverted pyramid form and an end face; and forming multiple quantum well layers on the end face, with each quantum well layer including an indium gallium nitride quantum well and a barrier layer. The indium gallium nitride quantum well is grown at a growth temperature adjusted using a trend equation within a temperature range of 480° C. to 810° C.Type: ApplicationFiled: September 26, 2023Publication date: February 27, 2025Inventors: I-KAI LO, CHENG-DA TSAI, YU-CHUNG LIN, YING-CHIEH WANG, MING-CHI CHOU, TING-CHANG CHANG
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Patent number: 12227646Abstract: A resin, including a compound having the following Formula 1-1: wherein n ranges from 1 to 5, and R1, R2, R3 and R4 are as defined herein.Type: GrantFiled: December 5, 2022Date of Patent: February 18, 2025Assignee: A.C.R. TECH CO., LTD.Inventors: Shih-Hao Liao, Min-Yuan Yang, Ya-Yen Chou, Jheng-Hong Ciou, Cheng-Chung Chen
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Patent number: 12227637Abstract: A benzoxazine resin, including a compound of the following Formula 1-1: where R1, R2, and R3 are as defined herein.Type: GrantFiled: December 6, 2022Date of Patent: February 18, 2025Assignee: A.C.R. TECH CO., LTD.Inventors: Shih-Hao Liao, Min-Yuan Yang, Ya-Yen Chou, Jheng-Hong Ciou, Cheng-Chung Chen
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Publication number: 20250047270Abstract: A delay calibration circuit includes a first delay chain, a second delay chain, and a calibration circuit. The first delay chain includes a plurality of first delay units and delays a clock signal with a first delay to generate a first delay signal. The supply current for each of the first delay units is a first current. The second delay chain includes a plurality of second delay units and a third delay unit. The second delay units delay a first signal with a second delay to generate a second delay signal. The third delay unit delays the second delay signal to generate the third delay signal. The supply current for each unit in the second delay chain is a second current. The calibration circuit adjusts a current ratio of the second current to the first current based on the second delay signal and the third delay signal.Type: ApplicationFiled: December 30, 2023Publication date: February 6, 2025Inventors: Cheng-Chung CHOU, Tu-Hsiu WANG, Cheng-Tao LI
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Publication number: 20130317754Abstract: A machine-implemented method for analyzing a genome-wide gene expression profiling includes: searching at least one pathway database using genes in the genome-wide gene expression profiling as an index to find pathways; screening the pathways according to expression levels of the genes in the genome-wide gene expression profiling for identifying screened pathways that have statistical significance; establishing pathway sets according to the genes associated with the screened pathways; and determining biological information of the genes that are common to the screened pathways in the pathway set by making reference to correlation between the genes and gene ontology terms.Type: ApplicationFiled: December 27, 2012Publication date: November 28, 2013Applicant: National Chung Cheng UniversityInventors: Cheng-Chung Chou, Chi- Wei Tseng
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Patent number: 8427542Abstract: An image calibration method includes: (a) sensing at least one target pixel of a sensing row from an effective pixel region of an image sensor to generate at least one target pixel value; (b) sensing at least one reference pixel of a shading region in the image sensor to generate a calibration value, wherein the reference pixel and the sensing row do not belong to the same row; and (c) referring to the calibration value to calibrate and output the target pixel value.Type: GrantFiled: August 18, 2009Date of Patent: April 23, 2013Assignee: PixArt Imaging Inc.Inventors: Cheng-Chung Chou, Yi-Hsien Ko, Wei-Ting Chan
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Publication number: 20100265335Abstract: An image calibration method includes: (a) sensing at least one target pixel of a sensing row from an effective pixel region of an image sensor to generate at least one target pixel value; (b) sensing at least one reference pixel of a shading region in the image sensor to generate a calibration value, wherein the reference pixel and the sensing row do not belong to the same row; and (c) referring to the calibration value to calibrate and output the target pixel value.Type: ApplicationFiled: August 18, 2009Publication date: October 21, 2010Inventors: Cheng-Chung Chou, Yi-Hsien Ko, Wei-Ting Chan
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Patent number: 7339225Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: GrantFiled: May 20, 2005Date of Patent: March 4, 2008Assignee: Faraday Technology Corp.Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Publication number: 20080032282Abstract: Molecular beacon for detecting an infection and/or expression or a mutation of a disease marker for diagnostics and pharmacogenomics. The molecular beacon is capable of hybridizing a disease-related RNA or DNA of a disease marker in a specimen obtained from a living subject, thereby emitting a signal detectable without a need for signal amplification. The disease marker includes a genetic sequence specific to a pathogen including a flu virus, a cancer cell marker, and a drug resistance-related genetic mutation marker for a drug resistant cancer and infectious pathogen. To detect a disease cell, a specimen containing one or more cells is obtained from a living subject, and fixed by an organic solvent. A molecular beacon is then added to the specimen, followed by staining nuclei of the cells in the specimen. The signal is detectable with a microscope, FACS scan, ELISA plate reader, Scanner, or any combinations thereof.Type: ApplicationFiled: December 22, 2006Publication date: February 7, 2008Applicant: AL Vitae PharmaceuticalsInventors: Augustine Lin, Pan-Chyr Yang, Cheng-Chung Chou
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Patent number: 7327551Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set includes a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: GrantFiled: November 19, 2006Date of Patent: February 5, 2008Assignee: Faraday Technology Corp.Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Patent number: 7282902Abstract: A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.Type: GrantFiled: March 7, 2004Date of Patent: October 16, 2007Assignee: Faraday Technology Corp.Inventors: Yuan-Hsun Chang, Jia-Jio Huang, Cheng-Chung Chou
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Publication number: 20070090429Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: ApplicationFiled: November 19, 2006Publication date: April 26, 2007Applicant: FARADAY TECHNOLOGY CORP.Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Publication number: 20060261439Abstract: A capacitor structure including a first electrode set and a second electrode set is provided. The first electrode set comprises a plurality of first stripe electrodes, which are parallel to each other, and a first coupling circuit. The first coupling circuit is coupled to a part of stripe electrodes, wherein the coupled first stripe electrodes and the uncoupled first stripe electrodes are alternately arranged. In addition, the second electrode set comprises a plurality of second stripe electrodes, which are parallel to each other, and a second coupling circuit. The second coupling circuit is coupled to a part of the second stripe electrodes, wherein the coupled second stripe electrodes and the uncoupled second stripe electrodes are alternately arranged. Furthermore, the coupled first stripe electrodes are coupled to the coupled second stripe electrodes, and the uncoupled first stripe electrodes are coupled to the uncoupled second stripe electrodes.Type: ApplicationFiled: May 17, 2005Publication date: November 23, 2006Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Publication number: 20060261394Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: ApplicationFiled: May 20, 2005Publication date: November 23, 2006Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Patent number: 6979983Abstract: A voltage regulator, regulating a supply voltage and outputting a regulated voltage. The voltage regulator comprises a two stage OP which outputs a first voltage and a second voltage according to a reference voltage and a feedback voltage. A NMOS transistor controlled by a voltage detection unit, to receive the second voltage when the detected supply voltage is in a high mode. A PMOS transistor controlled by the voltage detection unit, to receive the first voltage when the detected supply voltage is in a low mode. A feedback circuit for receiving the regulated voltage and outputting the feedback voltage to the two stage OP.Type: GrantFiled: April 28, 2004Date of Patent: December 27, 2005Assignee: Faraday Technology Corp.Inventors: Wen-Cheng Yen, Cheng-Chung Chou
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Publication number: 20050242794Abstract: A voltage regulator, regulating a supply voltage and outputting a regulated voltage. The voltage regulator comprises a two stage OP which outputs a first voltage and a second voltage according to a reference voltage and a feedback voltage. A NMOS transistor controlled by a voltage detection unit, to receive the second voltage when the detected supply voltage is in a high mode. A PMOS transistor controlled by the voltage detection unit, to receive the first voltage when the detected supply voltage is in a low mode. A feedback circuit for receiving the regulated voltage and outputting the feedback voltage to the two stage OP.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Inventors: Wen-Cheng Yen, Cheng-Chung Chou
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Publication number: 20050194953Abstract: A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.Type: ApplicationFiled: March 7, 2004Publication date: September 8, 2005Inventors: YUAN-HSUN CHANG, JIA-JIO HUANG, CHENG-CHUNG CHOU