Abstract: An illuminant shoe has a body, an outsole and an illuminating device. The body has a putting segment, a lifting cover and an insole. The putting segment has a heel lining and a through hole. The lifting cover is connected to the heel lining. The insole is mounted in the putting segment. The outsole is mounted on the putting segment and has a mounting chamber. The illuminating device is mounted in the mounting chamber and has an illuminating module, a controlling module and a switch. The illuminating module has first wires, multiple illuminating elements and a first electrical element. The controlling module is connected to the illuminating module and has two second electrical elements, multiple second wires, a controlling unit, a battery and a protecting casing. The switch is mounted in the putting segment, is connected to the controlling module and has a third wire and a third electrical element.

Abstract: An analog-to-digital converter includes a sample and hold unit, a successive control unit, a look-up memory, and a calibrating comparator, which further includes a positive input end, a negative input end, a timing signal input end, a data port, a latch unit, an enable switch, a first controllable resistor, a second controllable resistor, a reset switch assembly, a controllable capacitive device, and an output end.

Abstract: A low drop-out (LDO) voltage regulator with efficient frequency compensation is disclosed. The LDO voltage regulator includes an error amplifier, a transmission element, a voltage divider and a pole control unit. The error amplifier generates a control signal according to a reference voltage and a feedback voltage. The transmission element is coupled to the error amplifier, and adjusts an input voltage to generate an output voltage according to the control signal. The voltage divider is coupled to the transmission element, and performs a voltage division operation on the output voltage to generate the feedback voltage. The pole control unit is coupled to the transmission element, and provides and adjusts an output capacitor of the LDO voltage regulator to fix a frequency of a pole according to variation of an output impedance of the transmission element, so as to maintain loop stability.

Abstract: An optical disc drive includes a main body, a cover, an extension, and an elastic element. The cover includes a pivoting portion and is pivotably connected to the main body via the pivoting portion. The extension is connected to the pivoting portion. The cover is adapted for pivoting relative to the main body to drive the extension to move along a movement path. The elastic element is disposed on the main body and includes two first limiting portions opposite to each other. The movement path extends through a gap between the two first limiting portions. A distance between the two first limiting portions is smaller than an outer diameter of the extension.

Abstract: An analog-to-digital converter includes a sample and hold unit, a successive control unit, a look-up memory, and a calibrating comparator, which further includes a positive input end, a negative input end, a timing signal input end, a data port, a latch unit, an enable switch, a first controllable resistor, a second controllable resistor, a reset switch assembly, a controllable capacitive device, and an output end.

Abstract: A phase selector is disclosed. The phase selector is utilized for outputting an output clock to a flip-flop according to an input data signal latched by the flip-flop. The phase selector includes: a clock phase adjustor, for adjusting the delay of an input clock to generate a first clock and a second clock, wherein the clock phases of the first clock and the second clock are different; a phase detector, for detecting phase relation between the input data signal and the first clock to generate a detecting signal; a decision circuit, coupled to the phase detector, for generating a selecting signal according to the detecting signal; and a selection circuit, coupled to the decision circuit, for selecting the input clock or the second clock to generate the output clock to the flip-flop according to the selecting signal.

Abstract: An optical disc drive includes a main body, a cover, an extension, and an elastic element. The cover includes a pivoting portion and is pivotably connected to the main body via the pivoting portion. The extension is connected to the pivoting portion. The cover is adapted for pivoting relative to the main body to drive the extension to move along a movement path. The elastic element is disposed on the main body and includes two first limiting portions opposite to each other. The movement path extends through a gap between the two first limiting portions. A distance between the two first limiting portions is smaller than an outer diameter of the extension.

Abstract: An optical disc drive including a chassis, a circuit board and a traverse is provided. The traverse includes a carrier, a pick-up head module, a spindle motor module and a flexible flat cable. The carrier has an opening. The pick-up head module is movably disposed in the opening. The spindle motor module disposed on the carrier is located at one side of the pick-up head module. The flexible flat cable disposed in the opening has two connection ends respectively connected to the pick-up head module and the circuit board. The pick-up head module located at a first position enables the flexible flat cable to have a bending portion protruding towards a direction opposite to the position of the spindle motor module. The pick-up head module located at a second position extends the bending portion. The first position is closer to the spindle motor module than the second position is.

Abstract: The present invention provides a data latch circuit. The data latch circuit includes a first data latch unit, a second data latch unit, a third data latch unit, and a phase selector. The first data latch unit is used for latching a first input data according to a first clock signal and outputting a first output data. The second data latch unit is used for latching the first output data according to a second clock signal and outputting a second output data. The third data latch unit is used for latching the second output data according to a third clock signal and outputting an output data. The phase selector is coupled to the second data latch unit for generating the second clock signal to the second data latch unit according to phase relation between the first clock signal and the third clock signal.

Abstract: A fixing structure of battery module for fixing a battery module in an electronic device is proposed. The fixing structure includes a first lid and a second lid, which are formed on a surface of the electronic device, wherein the first lid is formed with a first fastening part, and the second lid is formed with a second fastening part for being engaged with the first fastening part; a mounting cavity formed in the electronic device at a position corresponding to the second lid; a first locking part formed on the second lid; and a second locking part formed on the battery module, for being coupled to the first locking part so as to fasten the battery module to the second lid. When the first and second lids are coupled together by the first and second fastening parts, the battery module fastened to the second lid is received in the mounting cavity and fixed in the electronic device.

Abstract: A track and hold circuit is disclosed, including: a source follower coupled to a voltage supply; a MOS transistor with well structure, the MOS transistor having a gate terminal coupled to a gate terminal of the source follower, a drain terminal coupled to its body terminal and a source terminal of the source follower, and a source terminal coupled to a current source and an output terminal; a capacitive device having a terminal coupled to the gate terminal of the MOS transistor and another terminal coupled to a fixed voltage level; and a switch device coupled and disposed between an input signal and the gate terminal of the MOS transistor, wherein the switch device is controlled by a control signal.

Abstract: A low drop-out (LDO) voltage regulator with efficient frequency compensation is disclosed. The LDO voltage regulator includes an error amplifier, a transmission element, a voltage divider and a pole control unit. The error amplifier generates a control signal according to a reference voltage and a feedback voltage. The transmission element is coupled to the error amplifier, and adjusts an input voltage to generate an output voltage according to the control signal. The voltage divider is coupled to the transmission element, and performs a voltage division operation on the output voltage to generate the feedback voltage. The pole control unit is coupled to the transmission element, and provides and adjusts an output capacitor of the LDO voltage regulator to fix a frequency of a pole according to variation of an output impedance of the transmission element, so as to maintain loop stability.

Abstract: A bandgap voltage generating circuit includes a circuit coupled to a first node and a second node, driving the first and the second nodes to the same voltage level. A first impedance element is coupled to the first node and a second impedance element is coupled to the second node, wherein the impedance of the second impedance element is larger than the impedance of the first impedance element. A first transistor is coupled to the first impedance element, and a second transistor is coupled to the second impedance element and the first transistor. The bandgap generating circuit generates a bandgap voltage at the second node.

Abstract: The present invention discloses a time-interleaved analog-to-digital converter (ADC), which includes a first and a second sub-ADC and a calibration module. The calibration module includes a switch module and a calibration engine. The switch module selectively provides one of a set of reference voltage levels, which are provided by a resistor series of the first sub-ADC, onto an input signal line, which is shared by the first and the second sub-ADCs. The calibration engine calibrates pre-amplifying units of the first and the second sub-ADCs according to digital signals generated by the first and the second sub-ADCs.

Abstract: A calibration device for calibrating an ADC comprising: an error estimator for estimating an error of a digital signal outputted from the ADC, the error estimator includes: a digital filter for filtering the digital signal to generate a filtered signal; and a least-mean-square module for performing a least-mean-square operation according to the filtered signal to generate an estimated error; and an error correction module for correcting the digital signal according to the estimated error.

Abstract: The present invention discloses a time-interleaved analog-to-digital converter (ADC), which includes a first and a second sub-ADC and a calibration module. The calibration module includes a switch module and a calibration engine. The switch module selectively provides one of a set of reference voltage levels, which are provided by a resistor series of the first sub-ADC, onto an input signal line, which is shared by the first and the second sub-ADCs. The calibration engine calibrates pre-amplifying units of the first and the second sub-ADCs according to digital signals generated by the first and the second sub-ADCs.

Abstract: A battery module fixture applicable to a battery module having a first positioning portion is disclosed. The battery module fixture includes a base and a spring member. The base includes a second positioning portion having a first end for engaging with the first positioning portion, and a second end connected to the first end capable of being fixed to the first positioning portion. The spring member is capable of being fixed to the base, and includes a third positioning portion corresponding to the first end of the second positioning portion of the base, and a actuating portion for moving along with the third positioning portion, so as to break the third positioning portion away from the first end.

Abstract: A track and hold circuit is disclosed, including: a source follower coupled to a voltage supply; a MOS transistor with well structure, the MOS transistor having a gate terminal coupled to a gate terminal of the source follower, a drain terminal coupled to its body terminal and a source terminal of the source follower, and a source terminal coupled to a current source and an output terminal; a capacitive device having a terminal coupled to the gate terminal of the MOS transistor and another terminal coupled to a fixed voltage level; and a switch device coupled and disposed between an input signal and the gate terminal of the MOS transistor, wherein the switch device is controlled by a control signal.

Abstract: This invention discloses a lock mechanism. The lock mechanism comprises a tray, a locking element, a solenoid, a linked apparatus, a first arm and a boss. The locking element has a protrusion and is rotably fixed on the tray. The solenoid is fixed on the tray and supplies a magnetic force to an active block. The linked apparatus is connected with the active block of the solenoid and is rotably fixed on the tray to push the locking element. The first arm is rotably fixed on the tray to push the linked apparatus and has a protruding rib to push against the protrusion of the locking element. The boss cooperates with the locking element when the tray is loaded. According to this mechanism, the sounds resulted from the locking element and the first arm are happened at the same time.

Abstract: The present invention provides a data latch circuit. The data latch circuit includes a first data latch unit, a second data latch unit, a third data latch unit, and a phase selector. The first data latch unit is used for latching a first input data according to a first clock signal and outputting a first output data. The second data latch unit is used for latching the first output data according to a second clock signal and outputting a second output data. The third data latch unit is used for latching the second output data according to a third clock signal and outputting an output data. The phase selector is coupled to the second data latch unit for generating the second clock signal to the second data latch unit according to phase relation between the first clock signal and the third clock signal.