Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A LED backlight driving circuit includes a plurality of driving integrated circuits coupled to a data transmission line and a plurality of selecting circuits respectively connected to the plurality of driving integrated circuits. In an addressing mode, the plurality of selecting circuits are used to select one driving integrated circuit from the plurality of driving integrated circuits to set an address. The plurality of driving integrated circuits can set addresses via input/output pins connected to LEDs. So a number of pins of the driving integrated circuit can be equal to or less than 4, which will rise a yield of the LED backlight driving circuit setting in a PCB or in a glass board.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: An integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration is disclosed. The chip has a conventional memory circuit portion and a control circuit portion. In operation as a single chip packaged configuration, the control circuit portion is inactive. In a multi-chip packaged configuration, the control circuit serves to prolong the activation of the currently addressed memory chip, while delaying the activation of the memory chip which is to be addressed in the next memory address cycle.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT is connected to and is shared by a plurality of bit lines (32 in the preferred embodiment) through a first column decoder 44/46U and is also connected to a plurality of page latches through a second column decoder 46L. Each page latch is connected to one corresponding output buffer through a third column decoder circuit 38/40/42. The page latches are grouped in a plurality of sub-pages. The QCLT performs high speed and high accuracy current-mode comparison and converts the result of comparison into binary codes. These codes are stored in Q-latches 36U-2. The QCLT functions as a current-mode analog-to-digital converter (ADC) which converts the memory cell current to binary codes.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT is connected to and is shared by a plurality of bit lines (32 in the preferred embodiment) through a first column decoder 44/46U and is also connected to a plurality of page latches through a second column decoder 46L. Each page latch is connected to one corresponding output buffer through a third column decoder circuit 38/40/42. The page latches are grouped in a plurality of sub-pages. The QCLT performs high speed and high accuracy current-mode comparison and converts the result of comparison into binary codes. These codes are stored in Q-latches 36U-2. The QCLT functions as a current-mode analog-to-digital converter (ADC) which converts the memory cell current to binary codes.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT is connected to and is shared by a plurality of bit lines (32 in the preferred embodiment) through a first column decoder 44/46U and is also connected to a plurality of page latches through a second column decoder 46L. Each page latch is connected to one corresponding output buffer through a third column decoder circuit 38/40/42. The page latches are grouped in a plurality of sub-pages. The QCLT performs high speed and high accuracy current-mode comparison and converts the result of comparison into binary codes. These codes are stored in Q-latches 36U-2. The QCLT functions as a current-mode analog-to-digital converter (ADC) which converts the memory cell current to binary codes.