Abstract: Provided in the present invention is a multi-element co-doped sodium-ion positive electrode material, which is characterized in that the phase of the positive electrode material is an O3 phase, the space group thereof is R-3m, and the chemical formula thereof is Na?MaLibCucTidO2+?, wherein M is at least one of Ni, Co, Mn, Cr, V, Al, Fe, B, Si, Mg and Zn, 0.5???1, ?0.1???0.1, 0<a<0.95, 0<b<0.25, 0<c<0.3, 0<d<0.6, a+b+c+d=1, and the charge neutrality condition is met. Also provided in the present invention is a preparation method for and the use of the multi-element co-doped sodium-ion positive electrode material.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: Described herein is a technique for establishing an overall company-level confidence score based on analyzing data from various data sources. The overall score is derived using a machine learned model that takes as input a set of sub-scores, with each sub-score representing a measure of how frequently a domain name occurs within the same data record as a company name. The model used to combine the several sub-scores is trained using training data that includes a variety of sub-scores for company and domain names that have already been verified to be associated with one another.

Abstract: An error handling method performed by a computing device, the computing device comprises at least one computing device component and a board management controller (BMC) coupled to the at least one computing device component, the method comprises the steps of a BMC detecting an error relating to at least one computing device component, the BMC determining from a database a technical specification to fix the error and generating information for accessing the technical specification. An error handling apparatus comprises a BMC and at least one computing device component coupled to the BMC. The BMC is configured to detect an error relating to the at least one computing device component, determine from in a database a technical specification to fix the error, and generate information for accessing the technical specification.

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Abstract: Disclosed are a self-adaptive assistance control device, a computer device and a storage medium for vehicle passing curve. The method comprises: step S10, according to signals from vehicle's sensors, identifying current bend types, and obtaining, corresponding to bend types, a lateral impact degree of the current vehicle according to a lateral acceleration; step S11, obtain an expected longitudinal acceleration based on the lateral impact degree; step S12, according to the expected longitudinal acceleration and a current actual longitudinal acceleration, determining an activation type for current bend assist control; and step S13, according to the activation type, cooperatively controlling an engine torque or/and an ESC braking intensity, so as to realize expected longitudinal control over the vehicle in the road curve.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Abstract: Methods and devices use in two-color measurement systems. The methods and devices include methods of making corrections, methods of calculating correction factors, fluorescence scanners, and microarray chips. The said methods and devices enable a user to correct fluorescence intensities for errors caused by the occurrence of FRET and/or cross-talk when two fluorophores are used in two-color fluorescence arrays.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Abstract: The present disclosure provides a nucleated red blood cell simulating particle, which may be leukocytes bound to a fluorescent-staining inhibitor capable of stably binding to the nucleus or a nucleic acid in a cell so as to reduce the binding capacity of the particles to a fluorescent dye during their detection. The present disclosure also provides a method for preparing nucleated red blood cell simulating particles, including the following steps: (a) obtaining purified leukocytes; (b) suspending the leukocytes in a cell treatment solution containing a fluorescent-staining inhibitor which stably binds to the nucleus or a nucleic acid in a cell, and (c) washing the obtained product. The present disclosure also provides a hematology control mixture containing the nucleated red blood cell simulating particles.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.