Patents by Inventor Cheng-En Ho

Cheng-En Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9744624
    Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 ?m for fine line width/pitch.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 29, 2017
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Jaen-Don Lan, Pin-Chung Lin, Chen-Rui Tseng, Cheng-En Ho, Yu-An Chen
  • Publication number: 20160374206
    Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 ?m for fine line width/pitch.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Jaen-Don Lan, PIN-CHUNG LIN, CHEN-RUI TSENG, CHENG-EN HO, YU-AN CHEN
  • Publication number: 20160372409
    Abstract: Disclosed is a circuit board structure, including the first, second and third metal layers sequentially stacked on the substrate from bottom to top and formed by the sputtering process, the chemical plating process and the electroplating process, respectively. The substrate includes the stop layer and the resin layer stacked on the stop layer. The stop layer includes a pattern having at least one contact region, which is not covered by the resin layer. The first, second and third metal layers have an etched circuit pattern, respectively, and each of the etched circuit patterns is provided out of the corresponding contact region and aligned to each other to expose part of the resin layer. The etched circuit pattern is used for electrical connection. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and more stable.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Jaen-Don Lan, PIN-CHUNG LIN, CHEN-RUI TSENG, CHENG-EN HO, YU-AN CHEN
  • Patent number: 9194822
    Abstract: An adjustable fixture structure for a 3D X-ray CT device is disclosed. Only the detected article is fixed on the fixture element of the adjustable fixture structure, may the adjustable connecting element slide with respect to the adjustable sliding trough and the fixture element slide with respect to the fixture sliding trough, so that the detected article is adjusted into within the detection range of the 3D X-ray CT device by using the adjustable connecting element and the fixture element. As such, the issues which a detected article is difficult to be oriented and positioned, a detection efficacy and result is poor, and the detected article might thus be damaged, may be well overcome.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: November 24, 2015
    Assignee: YUAN ZE UNIVERSITY
    Inventors: Cheng-En Ho, Cheng-Hsien Yang, Ling-Huang Hsu
  • Patent number: 9079272
    Abstract: A solder joint with a multilayer IMC structure is provided. The solder joint includes a Cu pad, a Sn-based solder, a first, a second, and a third IMC layer. The Cu pad is disposed opposite to the Sn-based solder. The first IMC layer is disposed between the Cu pad and the Sn-based solder. The first IMC layer is a Cu3Sn layer. The second IMC layer is disposed between the first IMC layer and the Sn-based solder. The second IMC layer is a (Cu1-x1-y1Nix1Pdy1)6Sn5 layer, wherein x1 is in the range between 0 and 0.15, and y1 is in the range between 0 and 0.02. The third IMC layer is disposed between the second IMC layer and the Sn-based solder. The third IMC layer is a (Cu1-x2-y2Nix2Pdy2)6Sn5 layer, wherein x2 is in the range between 0 and 0.4, y2 is in the range between 0 and 0.02, and x2>x1.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: July 14, 2015
    Assignee: Yuan Ze University
    Inventors: Cheng-En Ho, Shih-Ju Wang, Yu-Hui Wu
  • Publication number: 20150168316
    Abstract: An adjustable fixture structure for a 3D X-ray CT device is disclosed. Only the detected article is fixed on the fixture element of the adjustable fixture structure, may the adjustable connecting element slide with respect to the adjustable sliding trough and the fixture element slide with respect to the fixture sliding trough, so that the detected article is adjusted into within the detection range of the 3D X-ray CT device by using the adjustable connecting element and the fixture element. As such, the issues which a detected article is difficult to be oriented and positioned, a detection efficacy and result is poor, and the detected article might thus be damaged, may be well overcome.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: YUAN ZE UNIVERSITY
    Inventors: Cheng-En HO, Cheng-Hsien YANG, Ling-Huang HSU
  • Publication number: 20140126955
    Abstract: A solder joint with a multilayer IMC structure is provided. The solder joint includes a Cu pad, a Sn-based solder, a first, a second, and a third IMC layer. The Cu pad is disposed opposite to the Sn-based solder. The first IMC layer is disposed between the Cu pad and the Sn-based solder. The first IMC layer is a Cu3Sn layer. The second IMC layer is disposed between the first IMC layer and the Sn-based solder. The second IMC layer is a (Cu1-x1-y1Nix1Pdy1)6Sn5 layer, wherein x1 is in the range between 0 and 0.15, and y1 is in the range between 0 and 0.02. The third IMC layer is disposed between the second IMC layer and the Sn-based solder. The third IMC layer is a (Cu1-x2-y2Nix2Pdy2)6Sn5 layer, wherein x2 is in the range between 0 and 0.4, y2 is in the range between 0 and 0.02, and x2>x1.
    Type: Application
    Filed: February 27, 2013
    Publication date: May 8, 2014
    Applicant: YUAN ZE UNIVERSITY
    Inventors: Cheng-En Ho, Shih-Ju Wang, Yu-Hui Wu
  • Patent number: 8702878
    Abstract: A method for controlling the beta-tin crystal orientation in solder joints is provided. The method is suitable for joining metallization pads using a solder containing tin and silver. By adjusting the silver content in the solder within a specific range of equal to or more than 2.5 wt. % and less than 3.2 wt. %, the [001] axes of beta-tin crystals in the solder is aligned to be in the direction parallel with a solder/metallization pad interface substantially. Electromigration-induced solder deformations and metallization pad consumption can be significantly reduced when solder joints have such a microstructure. Additionally, the undesired Ag3Sn plates in the solder matrix can be avoided accordingly.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 22, 2014
    Assignee: Yuan Ze University
    Inventors: Cheng-En Ho, Bo-Zong Chen, Chih-Nan Chen
  • Publication number: 20130153646
    Abstract: The embodiment of the present invention relates to a method for suppressing Kirkendall voids formation in a solder joint. A solder alloy doped with 0.1˜0.7 weight percent (wt. %) of palladium (Pd) is utilized. Before soldering, the solder alloy is disposed on a copper (Cu) pad, possibly treated with a surface finish. Subsequently, the solder alloy is joined with the Cu pad, so as to form the solder joint with a Cu/Cu3Sn/(Cu,Pd)6Sn5/solder structure. The formation of Kirkendall voids at the Cu/Cu3Sn interface is greatly suppressed in the presence of Pd in the solder. As the amount of Pd doped is minimal, the properties and the processing conditions for soldering are not changed to a large extent, and the mechanical reliability of the solder joint is significantly improved. Therefore, the present invention is suitable for the microelectronic packaging applications.
    Type: Application
    Filed: April 10, 2012
    Publication date: June 20, 2013
    Applicant: YUAN ZE UNIVERSITY
    Inventor: Cheng-En Ho
  • Publication number: 20130008288
    Abstract: A method for controlling the beta-tin crystal orientation in solder joints is provided. The method is suitable for joining metallization pads using a solder containing tin and silver. By adjusting the silver content in the solder within a specific range of equal to or more than 2.5 wt. % and less than 3.2 wt. %, the [001] axes of beta-tin crystals in the solder is aligned to be in the direction parallel with a solder/metallization pad interface substantially. Electromigration-induced solder deformations and metallization pad consumption can be significantly reduced when solder joints have such a microstructure. Additionally, the undesired Ag3Sn plates in the solder matrix can be avoided accordingly.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 10, 2013
    Applicant: YUAN ZE UNIVERSITY
    Inventors: Cheng-En Ho, Bo-Zong Chen, Chih-Nan Chen
  • Patent number: 8207469
    Abstract: A method for inhibiting electromigration-induced phase segregation suitable for solder joint configurations used in a chip package is described as following. First, a chip package including a wiring board, a chip and numbers of solder joints is provided, wherein the chip is disposed on the wiring board, and the solder joints are disposed between the chip and the wiring board to electrically connect the chip to the wiring board. Next, a first current and a second current are alternately applied to a side of the solder joints, wherein flowing directions of the first current and the second current are opposite. The current density of the first current is 103˜105 A/cm2, and the current density of the second current is 103˜105 A/cm2.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: June 26, 2012
    Assignee: Yuan Ze University
    Inventors: Cheng-En Ho, Wei-Hsiang Wu
  • Patent number: 8092621
    Abstract: A method for inhibiting the growth of a nickel-copper-tin intermetallic (i.e. (Ni,Cu)3Sn4) layer at the (Cu,Ni)6Sn5/nickel interface of a solder joint is described as follows. A Sn—Ag—Cu solder alloy with a Cu-content of 0.5˜1 weight percent (wt. %) is provided. The solder alloy is disposed on a surface finish of a soldering pad, having a nickel-based metallization layer. A material of the solder alloy further includes palladium. The solder alloy is joined with the surface finish, so as to form the solder joint containing palladium that enables to inhibit the growth of the undesired (Ni,Cu)3Sn4 layer between the (Cu,Ni)6Sn5 and nickel in the subsequent use at temperatures ranging from 100° C. to 180° C.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: January 10, 2012
    Assignee: Yuan Ze University
    Inventors: Cheng-En Ho, Chi-Ming Lin
  • Patent number: 8049650
    Abstract: A method for testing a digital to analog converter, which operates in an undersampling environment, wherein signals of a tested DAC and a signal generator are modulated by a PWM device and then processed by a digital processing circuit to generate a digital signal, whereby is formed a low-speed equivalent ADC. The signal generator is provided by uniform-distribution random test patterns, and the signal generator generates an uniform-distribution random analog signal to the equivalent ADC. Thereby, the test error caused by the non-ideality of the signal generator is corrected, and the tested circuit can work in a full speed.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: November 1, 2011
    Assignee: National Yunlin University of Science and Technology
    Inventors: Chun-Wei Lin, Cheng-En Ho
  • Publication number: 20110227769
    Abstract: A method for testing a digital to analog converter, which operates in an undersampling environment, wherein signals of a tested DAC and a signal generator are modulated by a PWM device and then processed by a digital processing circuit to generate a digital signal, whereby is formed a low-speed equivalent ADC. The signal generator is provided by uniform-distribution random test patterns, and the signal generator generates an uniform-distribution random analog signal to the equivalent ADC. Thereby, the test error caused by the non-ideality of the signal generator is corrected, and the tested circuit can work in a full speed.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 22, 2011
    Inventors: Chun-Wei Lin, Cheng-En Ho
  • Publication number: 20110139314
    Abstract: A method for inhibiting the growth of a nickel-copper-tin intermetallic (i.e. (Ni,Cu)3Sn4) layer at the (Cu,Ni)6Sn5/nickel interface of a solder joint is described as follows. A Sn—Ag—Cu solder alloy with a Cu-content of 0.5˜1 weight percent (wt. %) is provided. The solder alloy is disposed on a surface finish of a soldering pad, having a nickel-based metallization layer. A material of the solder alloy further includes palladium. The solder alloy is joined with the surface finish, so as to form the solder joint containing palladium that enables to inhibit the growth of the undesired (Ni,Cu)3Sn4 layer between the (Cu,Ni)6Sn5 and nickel in the subsequent use at temperatures ranging from 100° C. to 180° C.
    Type: Application
    Filed: May 10, 2010
    Publication date: June 16, 2011
    Inventors: Cheng-En Ho, Chi-Ming Lin
  • Patent number: 7950565
    Abstract: A high speed ball shear machine is adapted for removing a metal bump fixed on a substrate. The high speed ball shear machine includes a fixing base, a shear tool, and a metal bump catcher. The substrate is fixed on the top surface of the fixing base. The shear tool is disposed above the top surface. The fixing base is adapted for being translated along a translation path relative to the shear tool, wherein the translation path is a straight path. When the fixing base translates along the path, the metal bump is driven to strike the shear tool so as to separate itself from the substrate. The metal bump catcher, which is adapted for catching the drop bump after the striking, is disposed on the side wall of the fixing base. The bump catcher has a fillister with a configuration depicted in the figures of this invention.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: May 31, 2011
    Assignee: Yuan Ze University
    Inventors: Cheng-En Ho, Han-Lin Chung
  • Publication number: 20100301100
    Abstract: A high speed ball shear machine is adapted for removing a metal bump fixed on a substrate. The high speed ball shear machine includes a fixing base, a shear tool, and a metal bump catcher. The substrate is fixed on the top surface of the fixing base. The shear tool is disposed above the top surface. The fixing base is adapted for being translated along a translation path relative to the shear tool, wherein the translation path is a straight path. When the fixing base translates along the path, the metal bump is driven to strike the shear tool so as to separate itself from the substrate. The metal bump catcher, which is adapted for catching the drop bump after the striking, is disposed on the side wall of the fixing base. The bump catcher has a fillister with a configuration depicted in the figures of this invention.
    Type: Application
    Filed: September 8, 2009
    Publication date: December 2, 2010
    Inventors: Cheng-En Ho, Han-Lin Chung
  • Publication number: 20100127047
    Abstract: A method of inhibiting a formation of palladium-nickel-tin (Pd—Ni—Sn) intermetallic in solder joints is described as follows. Firstly, a solder alloy is provided. Then, at least one of a trace of copper and a trace of zinc is doped into the solder alloy. Afterward, the solder alloy is disposed on the Pd-bearing surface finish, such as a Pd/Ni bi-layer or a Au/Pd/Ni tri-layer. Next, the solder alloy is soldered with the surface finish as solder joints. During the soldering, the Cu and Zn will incorporate into the soldering reaction, forming copper-palladium-nickel-tin intermetallic and zinc-palladium-nickel-tin intermetallic, replacing the Pd—Ni—Sn respectively. Consequently, the addition of Cu and/or Zn into solders will inhibit the undesirable Pd—Ni—Sn intermetallic to form in the solder joints.
    Type: Application
    Filed: January 13, 2009
    Publication date: May 27, 2010
    Applicant: Yuan Ze University
    Inventors: Cheng-En Ho, Wei-Hsiang Wu, Cheng-Shiuan Lin
  • Publication number: 20090294409
    Abstract: A method for inhibiting electromigration-induced phase segregation suitable for solder joint configurations used in a chip package is described as following. First, a chip package including a wiring board, a chip and numbers of solder joints is provided, wherein the chip is disposed on the wiring board, and the solder joints are disposed between the chip and the wiring board to electrically connect the chip to the wiring board. Next, a first current and a second current are alternately applied to a side of the solder joints, wherein flowing directions of the first current and the second current are opposite. The current density of the first current is 103˜105 A/cm2, and the current density of the second current is 103˜105 A/cm2.
    Type: Application
    Filed: June 2, 2008
    Publication date: December 3, 2009
    Applicant: Yuan Ze University
    Inventors: Cheng-En Ho, Wei-Hsiang Wu
  • Publication number: 20080280785
    Abstract: A fluidic nano/micro array chipset comprises a microarray filling chip and a nano/micro array stamping chip. There are a plurality of sample containers and a plurality of nano/micro channels on the top of the microarray filling chip, and a plurality of nano/micro-scaled micro filling holes on the bottom of the microarray filling chip. Each nano/micro channel is connected to one of the sample containers and leads the sample solution in that sample container to the corresponding micro filling hole. The nano/micro array stamp chip comprises a plurality of stamping heads arranged in an array pattern, with a body part of the stamp chip and a plurality of space channels forming hydrophobic areas. Each sample solution is stored in the body of the stamp chip, and is transported by the corresponding stamping head to the stamping part of this stamping head.
    Type: Application
    Filed: April 28, 2008
    Publication date: November 13, 2008
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Fan Gang Tseng, Cheng En Ho