Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: An interconnect structure for insertion loss reduction in signal transmission and a method thereof are disclosed. In an embodiment, an interconnect is formed on a substrate by chemical etching process, and when the interconnect is protected by photoresist in chemical etching process, the etching direction of etching solution is not oriented, so undercut areas are respectively formed on both sides of a bottom of the interconnect at contact of the interconnect and the substrate because of etching solution residue after the etching process. An included angle formed in the undercut area between the interconnect and the substrate is defined as an etch angle, and a length of the portion, exposing in the undercut area, of the substrate is defined as an etch length. Controlling sizes of the etch angle and the etch length can reduce an insertion loss in signal transmission.

Abstract: A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/ conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 ?m to 100 ?m. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius.

Abstract: A nanotwinned structure deposited on a surface of a substrate is provided. The nanotwinned structure includes at least one domain, and the domain includes a plurality of nanotwins. Each of the nanotwins possesses a faced-centered cubic (FCC) structure. The plurality of nanotwins are stacked along the [111] crystallographic axis. Less than 50% of a surface of the nanotwinned structure takes the (111) as the preferred orientation.

Abstract: A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 ?m to 100 ?m. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius.

Abstract: A nanotwinned structure deposited on a surface of a substrate is provided. The nanotwinned structure includes at least one domain, and the domain includes a plurality of nanotwins. Each of the nanotwins possesses a faced-centered cubic (FCC) structure. The plurality of nanotwins are stacked along the [111] crystallographic axis. Less than 50% of a surface of the nanotwinned structure takes the (111) as the preferred orientation.

Abstract: A high-speed electroplating method is provided. The high-speed electroplating method includes the following steps: providing a substrate containing a conductive layer on its surface; coating a dry-film photoresist on the conductive layer of the substrate, and patterning the dry-film photoresist; performing a pretreatment process to clean the substrate; disposing the substrate in an electroplating solution; turning on an ultrasonic oscillation machine to vibrate the electroplating solution, and turning on a jet flow device to agitate the electroplating solution, and performing a pre-electroplating process with a plating current density of 0.5 A/dm2 to 5 A/dm2, and then performing a high-speed electroplating process with a plating current density of 6 A/dm2 to 100 A/dm2; depositing a conductive pillar on areas without the dry-film photoresist; and removing the dry-film photoresist being coated on the conductive layer of the substrate.

Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 ?m for fine line width/pitch.

Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 ?m for fine line width/pitch.

Abstract: Disclosed is a circuit board structure, including the first, second and third metal layers sequentially stacked on the substrate from bottom to top and formed by the sputtering process, the chemical plating process and the electroplating process, respectively. The substrate includes the stop layer and the resin layer stacked on the stop layer. The stop layer includes a pattern having at least one contact region, which is not covered by the resin layer. The first, second and third metal layers have an etched circuit pattern, respectively, and each of the etched circuit patterns is provided out of the corresponding contact region and aligned to each other to expose part of the resin layer. The etched circuit pattern is used for electrical connection. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and more stable.

Abstract: An adjustable fixture structure for a 3D X-ray CT device is disclosed. Only the detected article is fixed on the fixture element of the adjustable fixture structure, may the adjustable connecting element slide with respect to the adjustable sliding trough and the fixture element slide with respect to the fixture sliding trough, so that the detected article is adjusted into within the detection range of the 3D X-ray CT device by using the adjustable connecting element and the fixture element. As such, the issues which a detected article is difficult to be oriented and positioned, a detection efficacy and result is poor, and the detected article might thus be damaged, may be well overcome.

Abstract: A solder joint with a multilayer IMC structure is provided. The solder joint includes a Cu pad, a Sn-based solder, a first, a second, and a third IMC layer. The Cu pad is disposed opposite to the Sn-based solder. The first IMC layer is disposed between the Cu pad and the Sn-based solder. The first IMC layer is a Cu3Sn layer. The second IMC layer is disposed between the first IMC layer and the Sn-based solder. The second IMC layer is a (Cu1-x1-y1Nix1Pdy1)6Sn5 layer, wherein x1 is in the range between 0 and 0.15, and y1 is in the range between 0 and 0.02. The third IMC layer is disposed between the second IMC layer and the Sn-based solder. The third IMC layer is a (Cu1-x2-y2Nix2Pdy2)6Sn5 layer, wherein x2 is in the range between 0 and 0.4, y2 is in the range between 0 and 0.02, and x2>x1.

Abstract: An adjustable fixture structure for a 3D X-ray CT device is disclosed. Only the detected article is fixed on the fixture element of the adjustable fixture structure, may the adjustable connecting element slide with respect to the adjustable sliding trough and the fixture element slide with respect to the fixture sliding trough, so that the detected article is adjusted into within the detection range of the 3D X-ray CT device by using the adjustable connecting element and the fixture element. As such, the issues which a detected article is difficult to be oriented and positioned, a detection efficacy and result is poor, and the detected article might thus be damaged, may be well overcome.

Abstract: A solder joint with a multilayer IMC structure is provided. The solder joint includes a Cu pad, a Sn-based solder, a first, a second, and a third IMC layer. The Cu pad is disposed opposite to the Sn-based solder. The first IMC layer is disposed between the Cu pad and the Sn-based solder. The first IMC layer is a Cu3Sn layer. The second IMC layer is disposed between the first IMC layer and the Sn-based solder. The second IMC layer is a (Cu1-x1-y1Nix1Pdy1)6Sn5 layer, wherein x1 is in the range between 0 and 0.15, and y1 is in the range between 0 and 0.02. The third IMC layer is disposed between the second IMC layer and the Sn-based solder. The third IMC layer is a (Cu1-x2-y2Nix2Pdy2)6Sn5 layer, wherein x2 is in the range between 0 and 0.4, y2 is in the range between 0 and 0.02, and x2>x1.

Abstract: A method for controlling the beta-tin crystal orientation in solder joints is provided. The method is suitable for joining metallization pads using a solder containing tin and silver. By adjusting the silver content in the solder within a specific range of equal to or more than 2.5 wt. % and less than 3.2 wt. %, the [001] axes of beta-tin crystals in the solder is aligned to be in the direction parallel with a solder/metallization pad interface substantially. Electromigration-induced solder deformations and metallization pad consumption can be significantly reduced when solder joints have such a microstructure. Additionally, the undesired Ag3Sn plates in the solder matrix can be avoided accordingly.

Abstract: The embodiment of the present invention relates to a method for suppressing Kirkendall voids formation in a solder joint. A solder alloy doped with 0.1˜0.7 weight percent (wt. %) of palladium (Pd) is utilized. Before soldering, the solder alloy is disposed on a copper (Cu) pad, possibly treated with a surface finish. Subsequently, the solder alloy is joined with the Cu pad, so as to form the solder joint with a Cu/Cu3Sn/(Cu,Pd)6Sn5/solder structure. The formation of Kirkendall voids at the Cu/Cu3Sn interface is greatly suppressed in the presence of Pd in the solder. As the amount of Pd doped is minimal, the properties and the processing conditions for soldering are not changed to a large extent, and the mechanical reliability of the solder joint is significantly improved. Therefore, the present invention is suitable for the microelectronic packaging applications.

Abstract: A method for controlling the beta-tin crystal orientation in solder joints is provided. The method is suitable for joining metallization pads using a solder containing tin and silver. By adjusting the silver content in the solder within a specific range of equal to or more than 2.5 wt. % and less than 3.2 wt. %, the [001] axes of beta-tin crystals in the solder is aligned to be in the direction parallel with a solder/metallization pad interface substantially. Electromigration-induced solder deformations and metallization pad consumption can be significantly reduced when solder joints have such a microstructure. Additionally, the undesired Ag3Sn plates in the solder matrix can be avoided accordingly.

Abstract: A method for inhibiting electromigration-induced phase segregation suitable for solder joint configurations used in a chip package is described as following. First, a chip package including a wiring board, a chip and numbers of solder joints is provided, wherein the chip is disposed on the wiring board, and the solder joints are disposed between the chip and the wiring board to electrically connect the chip to the wiring board. Next, a first current and a second current are alternately applied to a side of the solder joints, wherein flowing directions of the first current and the second current are opposite. The current density of the first current is 103˜105 A/cm2, and the current density of the second current is 103˜105 A/cm2.

Abstract: A method for inhibiting the growth of a nickel-copper-tin intermetallic (i.e. (Ni,Cu)3Sn4) layer at the (Cu,Ni)6Sn5/nickel interface of a solder joint is described as follows. A Sn—Ag—Cu solder alloy with a Cu-content of 0.5˜1 weight percent (wt. %) is provided. The solder alloy is disposed on a surface finish of a soldering pad, having a nickel-based metallization layer. A material of the solder alloy further includes palladium. The solder alloy is joined with the surface finish, so as to form the solder joint containing palladium that enables to inhibit the growth of the undesired (Ni,Cu)3Sn4 layer between the (Cu,Ni)6Sn5 and nickel in the subsequent use at temperatures ranging from 100° C. to 180° C.

Abstract: A method for testing a digital to analog converter, which operates in an undersampling environment, wherein signals of a tested DAC and a signal generator are modulated by a PWM device and then processed by a digital processing circuit to generate a digital signal, whereby is formed a low-speed equivalent ADC. The signal generator is provided by uniform-distribution random test patterns, and the signal generator generates an uniform-distribution random analog signal to the equivalent ADC. Thereby, the test error caused by the non-ideality of the signal generator is corrected, and the tested circuit can work in a full speed.