Patents by Inventor Cheng-Eng Daniel Chen

Cheng-Eng Daniel Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-via interconnect structure and method of manufacture
    Patent number: 9425150
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Fei Huang, Ming Xiang Li, Edward Wan, Jacob Chen, Dun-Nian Yaung, Cheng-Eng Daniel Chen
  • MULTI-VIA INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURE
    Publication number: 20150228584
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.
    Type: Application
    Filed: April 21, 2014
    Publication date: August 13, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Fei Huang, Ming Xiang Li, Edward Wan, Jacob Chen, Dun-Nian Yaung, Cheng-Eng Daniel Chen