Abstract: An output circuit provides both a positive and negative pulse output at a single output terminal in response to the receipt of a single trigger input pulse for triggering either negative-edge sensitive or positive-edge sensitive input stages of succeeding circuit elements. The circuit includes a latch responsive to the input trigger signal, and the output of the latch is coupled to the data input terminal of a first clocked flip-flop for setting the flip-flop upon receipt of the clock signal. The output of the first clocked fip-flop is coupled to the reset terminal of the latch to reset the output of the first clocked flip-flop to its initial state upon receipt of a second clock signal. The output circuit further includes a divide-by-2 flip-flop clocked by the opposite phase of the clock signal to provide a divided clock signal.