Abstract: A camera module includes a unitary element, an optical image lens assembly, a fixed member and a driving member. The unitary element has an object-side opening. The optical image lens assembly is disposed in a containing space and has an optical axis. The fixed member is for accommodating the unitary element and includes a base and a cover, and the cover has a through hole and is connected with the base. The driving member is for driving the unitary element to move relative to the fixed member. The unitary element includes a reverse inclined structure including at least two annular concave structures. The at least two annular concave structures are arranged in order from the object-side opening to an image side, wherein a sectional surface of each of the annular concave structures passing through the optical axis includes a valley point and two concave ends.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: Disclosed is an electronic device including a driving unit, a plurality of sub-pixel circuits and a plurality of control signal lines. Each of the plurality of sub-pixel circuits includes a first switching element and at least one light emitting element, and the sub-pixel circuits are electrically connected to the driving unit in parallel. The control signal lines are electrically connected to the sub-pixel circuits respectively.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: Integrated circuit (IC) structures and methods for forming the same are provided. An IC structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. The guard ring structure includes a plurality of guard ring layers. Each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. Sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: A power supply has a housing, a circuit board, a wire, and a wire securing assembly. The wire securing assembly has a base plate and a securing structure. The securing structure has a first plate and a second plate. A side edge of the first plate is connected to the base plate. The second plate is spaced apart from the first plate. The wire is mounted through and between the first plate and the second plate. The wire securing assembly is modified from the current insulating part, in which the original side plate extends and forms an additional part, or a bent structure is added on the original side plate, and thus the additional structures become the securing structure. Thus, the wire is prevented from moving under vibration or external force and contacting the blades of the fan, or keeps in a position in compliance with safety requirements.

Abstract: An image generation method obtains an original image. A character area, a background area, and a position of each flawless character in the original image are determined. The character area is segmented to obtain a first image of each flawless character. A background is removed from the first image to obtain a second image. First image processing is performed on the second image to obtain a third image. Second image processing is performed on the second image to obtain fourth images. Third image processing is performed on the fourth images respectively to obtain fifth images. A similarity between each fifth image and the third image is calculated. When the similarity is greater than a defect threshold, a background image is segmented. Brightness of the background image is adjusted. The target fourth image and adjusted background image are synthesized. The method can generate images with defective characters quickly.

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

Abstract: A metalens, a metalens set, and a method of image construction or decryption are disclosed. The metalens includes metastructures each having a shape and a height related to a resonant light wavelength of the metastructure, so that the metalens can present an incident light of the resonant light wavelength as a light shape or light pattern at a far-field position matching the resonant light wavelength. A metalens set formed by staking the metalenses vertically can present incident lights having different resonant wavelengths as light shapes, light patterns, or resolved images at far-field positions matching the resonant wavelengths. Image construction or decryption are achieved by combining resolved images of the resonant light wavelengths with non-resolved images of non-resonant light wavelengths so as to compose an overlay image, which is to be decomposed by the metalens or the metalens set so as to recover the resolved images.

Abstract: An imaging lens assembly has an optical axis, and includes a plurality of optical elements. The optical axis passes through the optical elements, and the optical elements include a radial reduction lens element and a radial reduction light blocking element. The radial reduction lens element includes an optical effective portion and a peripheral portion. The peripheral portion is disposed around the optical effective portion along a circumferential direction of the optical axis. The radial reduction light blocking element includes a central opening and a radial reduction part. The optical axis passes through the central opening. The radial reduction part is reduced towards the optical axis along a direction vertical to the optical axis, so that the central opening is non-circular. The radial reduction part includes a plurality of light blocking structures. The light blocking structures are arranged along the direction vertical to the optical axis.

Abstract: An electric motor includes a motor main body and an inverter. The inverter is axially stacked on one end of the motor main body, and the inverter includes a gate driver, a control circuit, a capacitor module, a DC bus bar, a plurality of power modules and a plurality of AC bus bars. The power module includes a plurality of AC output terminals, a plurality of DC input terminals and a plurality of signal terminals, and the AC bus bars are respectively connected to corresponding AC output terminals and extend downward to a motor coil of the motor main body. The power modules and the corresponding DC input terminals are annularly arranged around the capacitor module, the DC bus bar is extended and electrically connected to the corresponding DC input terminals and the capacitor module.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: A communication device respectively establishes a plurality of wireless communication connections with a plurality of predetermined devices in an infrastructure network, and includes a wireless transceiver and a processor. The wireless transceiver transmits or receives wireless signals. The processor selects a spatial reuse mechanism, generates spatial reuse information according to the spatial reuse mechanism, and transmits at least one packet carrying the spatial reuse information to the predetermined devices. The spatial reuse information defines a pattern of a communication period. The communication period comprises a spatial reuse phase and a non-spatial reuse phase. The spatial reuse information comprises time information of at least one of the spatial reuse phase and the non-spatial reuse phase. In response to a selection of the spatial reuse mechanism, the processor suspends a wireless signal transmission with the predetermined devices during the spatial reuse phase.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.