Patents by Inventor Cheng-Fu F. Tsai

Cheng-Fu F. Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9740495
    Abstract: A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chen Guo, John Ho, Ziad Saliba, Arash Shokouhbakhsh, Cheng-Fu F. Tsai
  • Patent number: 9569222
    Abstract: A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chen Guo, John Ho, Ziad Saliba, Arash Shokouhbakhsh, Cheng-Fu F. Tsai
  • Publication number: 20150363206
    Abstract: A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions.
    Type: Application
    Filed: February 20, 2015
    Publication date: December 17, 2015
    Inventors: Chen Guo, John Ho, Ziad Saliba, Arash Shokouhbakhsh, Cheng-Fu F. Tsai
  • Publication number: 20150363205
    Abstract: A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Inventors: Chen Guo, John Ho, Ziad Saliba, Arash Shokouhbakhsh, Cheng-Fu F. Tsai