Patents by Inventor Cheng-Han Sung

Cheng-Han Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180366546
    Abstract: A semiconductor device includes a fin-like structure. The fin-like structure includes a bottom layer formed of silicon and at least a top layer formed of germanium. The semiconductor device further includes a gate stack feature overlaying a central upper portion of the fin-like structure, wherein the gate stack is in contact with a top surface and sidewalls of the top layer, and at least part of sidewalls of the bottom layer.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Cheng-Han SUNG, Ya-Tang Chiang
  • Patent number: 9041608
    Abstract: A portable electronic device includes a casing unit, a first support unit, a second support unit, a first antenna unit, a second antenna unit, a first conducting unit and a second conducting unit. The casing unit includes a first outer casing and a second outer casing pivotally connected with the first outer casing. The first outer casing includes a hinge structure pivotally connected with the second outer casing. The first support unit includes a first support body disposed in the hinge structure, and the second support unit includes a second support body disposed in the hinge structure. The first antenna unit includes a first antenna structure disposed on the first support body and separated from the second outer casing. The second antenna unit includes a second antenna structure disposed on the second support body and separated from the second outer casing.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: May 26, 2015
    Assignee: INPAQ TECHNOLOGY CO., LTD.
    Inventors: Yan-Ming Hong, Po-Chun Huang, Cheng-Han Sung, Chih-Wei Chen
  • Publication number: 20140015714
    Abstract: A portable electronic device includes a casing unit, a first support unit, a second support unit, a first antenna unit, a second antenna unit, a first conducting unit and a second conducting unit. The casing unit includes a first outer casing and a second outer casing pivotally connected with the first outer casing. The first outer casing includes a hinge structure pivotally connected with the second outer casing. The first support unit includes a first support body disposed in the hinge structure, and the second support unit includes a second support body disposed in the hinge structure. The first antenna unit includes a first antenna structure disposed on the first support body and separated from the second outer casing. The second antenna unit includes a second antenna structure disposed on the second support body and separated from the second outer casing.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: YAN-MING HONG, PO-CHUN HUANG, CHENG-HAN SUNG, CHIH-WEI CHEN
  • Publication number: 20080208944
    Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).
    Type: Application
    Filed: May 6, 2008
    Publication date: August 28, 2008
    Inventors: Cheng-Han Sung, Chein-Wei Jen, Chih-Wei Liu, Hung-Chi Lai, Gin-Kou Ma
  • Publication number: 20040243656
    Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).
    Type: Application
    Filed: January 7, 2004
    Publication date: December 2, 2004
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Han Sung, Chein-Wei Jen, Chih-Wei Liu, Hung-Chi Lai, Gin-Kou Ma