Patents by Inventor Cheng-Han Yang

Cheng-Han Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456383
    Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
  • Publication number: 20220273583
    Abstract: The disclosure provides a method for delivering an agent to posterior segment of an eye comprising administrating a pharmaceutical composition comprising the agent and mesoporous silica nanoparticles to the eye. An eye drop and a method for treating an ocular disease in a subject in need of such treatment are also provided.
    Type: Application
    Filed: February 25, 2022
    Publication date: September 1, 2022
    Inventors: CHENG-HSUN WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, TIEN-CHUN YANG, CHUNG-YUAN MOU, HARDY WAI HONG CHAN
  • Patent number: 11404574
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Publication number: 20220165941
    Abstract: A magnetic field sensor structure and a method for fabricating the magnetic field sensor structure are disclosed. The magnetic field sensor structure includes at least a magnetoresistive sensor assembly and a transistor assembly, which integrated on a single chip. The transistor assembly includes at least a semiconductor device and a first interconnect. The first interconnect is operably connected to the semiconductor device. The method includes depositing a dielectric layer on the transistor assembly. The method includes removing portions of the dielectric layer to form a first trench that exposes the first interconnect. The method includes performing a damascene process to form an ultra-thick metal (UTM) layer within the first trench to create a first metal coil. The first metal coil is configured as a first reset component. The method includes depositing another dielectric layer on the first metal coil. The method includes forming a flux guide within the another dielectric layer.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: Phillip Mather, Cheng-Han Yang
  • Publication number: 20220045073
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 10, 2022
    Inventors: Chin-Ling HUANG, Jhen-Yu TSAI, Cheng-Han YANG, Yi-Ju CHEN
  • Patent number: 11244950
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 8, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Jhen-Yu Tsai, Cheng-Han Yang, Yi-Ju Chen
  • Patent number: 11158505
    Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Publication number: 20210134864
    Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Patent number: 10937819
    Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 2, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Publication number: 20200379526
    Abstract: An electronic device can include a frame configured to receive and support an electronic component, a shell defining an internal volume sized to encompass the frame and the electronic component, the shell being slidably removable from the frame, the electronic component positioned within the internal volume and including an aperture, and a sealing member including a seal body and a compressible lip extending from the seal body, the sealing member at least partially surrounding the electronic component. The compressible lip is oriented such that the shell compresses the lip in a direction against the seal body at a first position adjacent to the electronic component and in the direction against the seal body at a second position adjacent to the electronic component opposite the first position.
    Type: Application
    Filed: September 27, 2019
    Publication date: December 3, 2020
    Inventors: Bart K. Andre, Edward J. Cooper, Brett W. Degner, Houtan R. Farahani, Steven A. Gerasimoff, William H. Greenbaum, James T. Handy, Daniel D. Hershey, PengYuan Huang, Eric A. Knopf, Richard D. Kosoglow, Mariel L. Lanas, Michael E. Leclerc, Michael D. McBroom, Rodrigo Dutervil Mubarak, David C. Parell, Sabrina K. Paseman, Eric R. Prather, Jacob W. Rutheiser, Christopher G. Siegel, Cheng-Han Yang, James M. Cuseo, Francesco Ferretti
  • Publication number: 20200126787
    Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Publication number: 20200075648
    Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 5, 2020
    Applicant: Powerchip Technology Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Patent number: 10522349
    Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Publication number: 20190164745
    Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 30, 2019
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Patent number: 9879177
    Abstract: The present invention relates inter alia to a new class of heteroleptic metal complexes comprising condensed aromatic heterocyclic rings, their preparation and use.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: January 30, 2018
    Assignee: Merck Patent GmbH
    Inventors: Susanne Heun, Nils Koenen, Cheng-Han Yang, Luisa De Cola
  • Patent number: 9396742
    Abstract: A magnetic read transducer including a magnetoresistive sensor is described, as well as a fabrication method thereof. The magnetoresistive sensor includes a cap layer overlaying a free layer. The cap layer is situated with a first thickness to absorb boron from the free layer. The magnetoresistive sensor is annealed, and boron is diffused from the free layer and absorbed by the cap layer, improving the magnetic performance of the free layer. The cap layer thickness is then reduced to a second thickness, thereby reducing the shield-to-shield (SS) stack spacing of the magnetoresistive sensor and allowing for increased areal recording density.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: July 19, 2016
    Assignee: Western Digital (Fremont), LLC
    Inventors: Cheng-Han Yang, Chen-Jung Chen, Christian Kaiser, Yuankai Zheng, Qunwen Leng, Mahendra Pakala
  • Patent number: 9257793
    Abstract: An electrical connector includes a body, two rows of terminals, and a grounding sheet. The body has a base and a tongue extending forwards from the base. The two rows of terminals are disposed in the tongue. At least one row of terminals includes a differential signal terminal pair and a grounding terminal that are disposed neighboring to each other. The grounding sheet is disposed in the tongue and located between the two rows of terminals. The grounding sheet has an open slot located between the differential signal terminal pair and the grounding terminal that are in the same row.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 9, 2016
    Assignee: LINTES TECHNOLOGY CO., LTD
    Inventors: Wei Zen Lo, Shih Chi Kuan, Cheng Han Yang
  • Patent number: 9070381
    Abstract: A method and system provide a magnetic transducer including a first shield, a read sensor, and a second shield. The read sensor is between the first shield and the second shield. The read sensor has a free layer including a plurality of ferromagnetic layers interleaved with and sandwiching at least one additional layer. Each of the ferromagnetic layers includes at least one of Fe, Co and B and has a first corrosion resistance. The additional layer(s) have a second corrosion resistance greater than the first corrosion resistance.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: June 30, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Cheng-Han Yang, Christian Kaiser, Yuankai Zheng, Qunwen Leng, Chih-Ching Hu
  • Patent number: 9064534
    Abstract: A method is provided for providing a magnetic recording transducer having a pinning layer with high pinning field stability. A bottom structure comprising a substrate, a magnetic shield above the substrate, a magnetic seed layer above the shield, a nonmagnetic spacer layer above the magnetic seed layer, and a layer of antiferromagnetic (AFM) material on the nonmagnetic spacer layer is provided. The bottom structure is heated to a temperature of at least 373 Kelvin (K) and then the bottom structure is cooled until the temperature of the structure is reduced to less than 293K. A pinned layer is deposited on the AFM layer, a nonmagnetic spacer is provided on the pinned layer, and a read sensor fabricated above the nonmagnetic spacer. In one embodiment, cooling the structure comprises reducing the temperature of the structure by at least 100K in less than 25 minutes.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: June 23, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Yuankai Zheng, Qunwen Leng, Cheng-Han Yang
  • Patent number: 9053719
    Abstract: A magnetic read transducer including a magnetoresistive sensor is described, as well as a fabrication method thereof. The magnetoresistive sensor includes a cap layer overlaying a free layer. The cap layer is situated with a first thickness to absorb boron from the free layer. The magnetoresistive sensor is annealed, and boron is diffused from the free layer and absorbed by the cap layer, improving the magnetic performance of the free layer. The cap layer thickness is then reduced to a second thickness, thereby reducing the shield-to-shield (SS) stack spacing of the magnetoresistive sensor and allowing for increased areal recording density.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: June 9, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Cheng-Han Yang, Chen-Jung Chien, Christian Kaiser, Yuankai Zheng, Qunwen Leng, Mahendra Pakala