Patents by Inventor Cheng-Han Yang

Cheng-Han Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930781
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Publication number: 20210050433
    Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. MORE, Shih-Chieh CHANG, Cheng-Han LEE, Huai-Tei YANG
  • Patent number: 10879124
    Abstract: The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Huai-Tei Yang, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20200379526
    Abstract: An electronic device can include a frame configured to receive and support an electronic component, a shell defining an internal volume sized to encompass the frame and the electronic component, the shell being slidably removable from the frame, the electronic component positioned within the internal volume and including an aperture, and a sealing member including a seal body and a compressible lip extending from the seal body, the sealing member at least partially surrounding the electronic component. The compressible lip is oriented such that the shell compresses the lip in a direction against the seal body at a first position adjacent to the electronic component and in the direction against the seal body at a second position adjacent to the electronic component opposite the first position.
    Type: Application
    Filed: September 27, 2019
    Publication date: December 3, 2020
    Inventors: Bart K. Andre, Edward J. Cooper, Brett W. Degner, Houtan R. Farahani, Steven A. Gerasimoff, William H. Greenbaum, James T. Handy, Daniel D. Hershey, PengYuan Huang, Eric A. Knopf, Richard D. Kosoglow, Mariel L. Lanas, Michael E. Leclerc, Michael D. McBroom, Rodrigo Dutervil Mubarak, David C. Parell, Sabrina K. Paseman, Eric R. Prather, Jacob W. Rutheiser, Christopher G. Siegel, Cheng-Han Yang, James M. Cuseo, Francesco Ferretti
  • Patent number: 10840358
    Abstract: Semiconductor structures and method for forming the same are provide. The method includes forming a gate structure over a substrate and forming a recess in the substrate adjacent to the gate structure. The method further includes forming a doped region at a sidewall and a bottom surface of the recess and partially removing the doped region to modify a shape of the recess. The method further includes forming a source/drain structure over a remaining portion of the doped region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
  • Patent number: 10811578
    Abstract: A LED carrier includes a substrate, a conductive layer, an adhesive layer, and a reflector. The conductive layer is disposed on the substrate, and has a bonding portion and an extending portion. The bonding portion has a top surface higher than a top surface of the extending portion. The adhesive layer covers the extending portion of the conductive layer and exposes the bonding portion of the conductive layer. The reflector is disposed over the adhesive layer. The adhesive layer has a hook portion in contact with a corner of the reflector.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 20, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chih-Hao Lin, Chun-Peng Lin, Chang-Han Chen, Kuang-Neng Yang, Cheng-Ta Kuo
  • Patent number: 10811761
    Abstract: A tag antenna structure of an information carrier includes a carrying sheet and a tag antenna disposed on the carrying sheet. An outer lateral edge of the carrying sheet is symmetrical to a first central axis, and a distance between the outer lateral edge of the carrying sheet and the first central axis is defined as a first outer radius. The tag antenna includes an annular segment and two extending segments respectively extending from two end portions of the annular segment. An outer lateral edge of the annular segment is symmetrical to a second central axis, and a distance between the outer lateral edge of the annular segment and the second central axis is defined as a second outer radius that is smaller than the first outer radius. The second central axis and the first central axis have an offset distance there-between that is larger than zero.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 20, 2020
    Assignee: AUDEN TECHNO CORP.
    Inventors: Chang-Fa Yang, An-Yao Hsiao, Chen-Pang Chao, Cheng-Han Tsai
  • Publication number: 20200313052
    Abstract: A LED carrier includes a substrate, a conductive layer, an adhesive layer, and a reflector. The conductive layer is disposed on the substrate, and has a bonding portion and an extending portion. The bonding portion has a top surface higher than a top surface of the extending portion. The adhesive layer covers the extending portion of the conductive layer and exposes the bonding portion of the conductive layer. The reflector is disposed over the adhesive layer. The adhesive layer has a hook portion in contact with a corner of the reflector.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Chih-Hao LIN, Chun-Peng LIN, Chang-Han CHEN, Kuang-Neng YANG, Cheng-Ta KUO
  • Publication number: 20200303548
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20200285277
    Abstract: A motor assembly is provided. The motor assembly includes a motor, a driving force transmission module, and a driving force output component. The motor includes a rotating shaft, the rotating shaft is configured to rotate along a first axis. The driving force transmission module includes a first transmission portion and a second transmission portion connected with each other. The first transmission portion is connected with the rotating shaft of the motor, and the second transmission portion is bent relative to the first transmission portion and extends to one side of the motor. The driving force output component is connected with an end of the second transmission portion away from the first transmission portion, and configured to rotate along a second axis, which is parallel to the first axis.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventors: Chui-Hung CHEN, Cheng-Han CHUNG, Ching-Yuan YANG, Chia-Min CHENG
  • Publication number: 20200288002
    Abstract: A functional assembly and an electronic device including the functional assembly are provided. The functional assembly includes a functional module, a motor, and a linking mechanism. The functional module has a first shaft. The motor has a second shaft and is configured to drive the second shaft to rotate. The linking mechanism is connected with the first shaft and the second shaft such that the first shaft and the second shaft are linking-up with each other. As a result, the thickness of the electronic device near the frame is not limited by the size of the motor, which further reduces the thickness of the electronic device.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventors: Cheng-Han CHUNG, Chui-Hung CHEN, Chia-Min CHENG, Ching-Yuan YANG
  • Patent number: 10680106
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20200152742
    Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei YANG, Zheng-Yang PAN, Shih-Chieh CHANG, Chun-Chieh WANG, Cheng-Han Lee
  • Publication number: 20200126787
    Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Publication number: 20200111911
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Publication number: 20200106154
    Abstract: A tag antenna structure of an information carrier includes a carrying sheet and a tag antenna disposed on the carrying sheet. An outer lateral edge of the carrying sheet is symmetrical to a first central axis, and a distance between the outer lateral edge of the carrying sheet and the first central axis is defined as a first outer diameter. The tag antenna includes an annular segment and two extending segments respectively extending from two end portions of the annular segment. An outer lateral edge of the annular segment is symmetrical to a second central axis, and a distance between the outer lateral edge of the annular segment and the second central axis is defined as a second outer diameter that is smaller than the first outer diameter. The second central axis and the first central axis have an offset distance there-between that is larger than zero.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 2, 2020
    Inventors: CHANG-FA YANG, An-Yao Hsiao, Chen-Pang Chao, Cheng-Han Tsai
  • Publication number: 20200080942
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Application
    Filed: March 16, 2018
    Publication date: March 12, 2020
    Applicant: iXensor CO., LTD.
    Inventors: Yenyu CHEN, An Cheng CHANG, Tai I CHEN, Su Tung YANG, Chih Jung HSU, Chun Cheng LIN, Min Han WANG, Shih Hao CHIU
  • Publication number: 20200075648
    Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 5, 2020
    Applicant: Powerchip Technology Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Publication number: 20200059542
    Abstract: A functional assembly is provided. The functional assembly includes a functional module and a lifting assembly. The lifting assembly is fixed in the housing and configured to drive the functional module to move. In addition, the functional assembly further includes a rotating assembly. The rotating assembly is connected to the functional module.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Inventors: Chui-Hung CHEN, Ching-Yuan YANG, Cheng-Han CHUNG, Chia-Min CHENG
  • Patent number: D884689
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: May 19, 2020
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Chui-Hung Chen, Zih-Siang Huang, Hung-Chieh Wu, Liang-Jen Lin, Ching-Yuan Yang, Cheng-Han Chung, Chia-Min Cheng