Abstract: A magnetic field sensor structure includes a magnetoresistive sensor assembly and a transistor assembly. A dielectric layer is deposited on the transistor assembly. The dielectric layer includes a trench that exposes an interconnect of the transistor assembly. A damascene process is performed to form an ultra-thick metal (UTM) layer within the trench to create a first metal coil. The first metal coil is configured as a first reset component. Another dielectric layer is formed on the first metal coil. A flux guide is formed within the another dielectric layer. A second metal coil is formed over the another dielectric layer. The second metal coil is configured as a second reset component. The first reset component and the second reset component are configured as a reset mechanism, which is responsive to the transistor assembly and operable to magnetize the flux guide to a predetermined orientation.

Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.

Abstract: A magnetic field sensor structure and a method for fabricating the magnetic field sensor structure are disclosed. The magnetic field sensor structure includes at least a magnetoresistive sensor assembly and a transistor assembly, which integrated on a single chip. The transistor assembly includes at least a semiconductor device and a first interconnect. The first interconnect is operably connected to the semiconductor device. The method includes depositing a dielectric layer on the transistor assembly. The method includes removing portions of the dielectric layer to form a first trench that exposes the first interconnect. The method includes performing a damascene process to form an ultra-thick metal (UTM) layer within the first trench to create a first metal coil. The first metal coil is configured as a first reset component. The method includes depositing another dielectric layer on the first metal coil. The method includes forming a flux guide within the another dielectric layer.

Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.

Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.

Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.

Abstract: An electronic device can include a frame configured to receive and support an electronic component, a shell defining an internal volume sized to encompass the frame and the electronic component, the shell being slidably removable from the frame, the electronic component positioned within the internal volume and including an aperture, and a sealing member including a seal body and a compressible lip extending from the seal body, the sealing member at least partially surrounding the electronic component. The compressible lip is oriented such that the shell compresses the lip in a direction against the seal body at a first position adjacent to the electronic component and in the direction against the seal body at a second position adjacent to the electronic component opposite the first position.

Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.

Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.

Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.

Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.

Abstract: The present invention relates inter alia to a new class of heteroleptic metal complexes comprising condensed aromatic heterocyclic rings, their preparation and use.

Abstract: A magnetic read transducer including a magnetoresistive sensor is described, as well as a fabrication method thereof. The magnetoresistive sensor includes a cap layer overlaying a free layer. The cap layer is situated with a first thickness to absorb boron from the free layer. The magnetoresistive sensor is annealed, and boron is diffused from the free layer and absorbed by the cap layer, improving the magnetic performance of the free layer. The cap layer thickness is then reduced to a second thickness, thereby reducing the shield-to-shield (SS) stack spacing of the magnetoresistive sensor and allowing for increased areal recording density.

Abstract: An electrical connector includes a body, two rows of terminals, and a grounding sheet. The body has a base and a tongue extending forwards from the base. The two rows of terminals are disposed in the tongue. At least one row of terminals includes a differential signal terminal pair and a grounding terminal that are disposed neighboring to each other. The grounding sheet is disposed in the tongue and located between the two rows of terminals. The grounding sheet has an open slot located between the differential signal terminal pair and the grounding terminal that are in the same row.

Abstract: A method and system provide a magnetic transducer including a first shield, a read sensor, and a second shield. The read sensor is between the first shield and the second shield. The read sensor has a free layer including a plurality of ferromagnetic layers interleaved with and sandwiching at least one additional layer. Each of the ferromagnetic layers includes at least one of Fe, Co and B and has a first corrosion resistance. The additional layer(s) have a second corrosion resistance greater than the first corrosion resistance.

Abstract: A method is provided for providing a magnetic recording transducer having a pinning layer with high pinning field stability. A bottom structure comprising a substrate, a magnetic shield above the substrate, a magnetic seed layer above the shield, a nonmagnetic spacer layer above the magnetic seed layer, and a layer of antiferromagnetic (AFM) material on the nonmagnetic spacer layer is provided. The bottom structure is heated to a temperature of at least 373 Kelvin (K) and then the bottom structure is cooled until the temperature of the structure is reduced to less than 293K. A pinned layer is deposited on the AFM layer, a nonmagnetic spacer is provided on the pinned layer, and a read sensor fabricated above the nonmagnetic spacer. In one embodiment, cooling the structure comprises reducing the temperature of the structure by at least 100K in less than 25 minutes.

Abstract: A magnetic read transducer including a magnetoresistive sensor is described, as well as a fabrication method thereof. The magnetoresistive sensor includes a cap layer overlaying a free layer. The cap layer is situated with a first thickness to absorb boron from the free layer. The magnetoresistive sensor is annealed, and boron is diffused from the free layer and absorbed by the cap layer, improving the magnetic performance of the free layer. The cap layer thickness is then reduced to a second thickness, thereby reducing the shield-to-shield (SS) stack spacing of the magnetoresistive sensor and allowing for increased areal recording density.

Abstract: The present invention relates inter alia to a new class of heteroleptic metal complexes comprising condensed aromatic heterocyclic rings, their preparation and use.