Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Abstract: An extreme ultraviolet (EUV) photolithography system cleans debris from an EUV reticle. The system includes a cleaning electrode configured to be positioned adjacent the EUV reticle. The system includes a voltage source that helps draw debris from the EUV reticle toward the cleaning electrode by applying a voltage of alternating polarity to the cleaning electrode.

Abstract: A system includes a microphone unit coupled to a roof of an autonomous vehicle. The microphone unit includes a microphone board having a first opening. The microphone unit also includes a first microphone positioned over the first opening and coupled to the microphone board. The microphone unit further includes an accelerometer. The system also includes a processor coupled to the microphone unit.

Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.

Abstract: A wafer cassette for receiving a wafer is provided. The wafer cassette includes a cassette housing, a first supporting rib and a second supporting rib. The first supporting rib is disposed in the cassette housing, wherein the first supporting rib includes a front supporting portion, a middle supporting portion and a rear supporting portion, the front supporting portion is connected to one end of the middle supporting portion, the rear supporting portion is connected to the other end of the middle supporting portion, and the front supporting portion has a front curved edge. The second supporting rib is disposed in the cassette housing. An edge portion of the wafer is supported by the first supporting rib and the second supporting rib, and the front supporting portion, the middle supporting portion and the rear supporting portion contact the wafer simultaneously.

Abstract: A lutein-containing ophthalmic composition, wherein the ophthalmic composition is mainly consisting of a natural anti-inflammatory substance, a substance with increasing liquid viscosity, and an artificial tear. The substance with increasing liquid viscosity could apply the ophthalmic composition to elongate the retention time on the ocular surface, thereby increasing the retention time of anti-inflammatory substance on the ocular surface for treating dry eye syndrome and inhibiting ocular surface inflammation.

Abstract: A power converter including switch components having different safe operating areas is provided. A first terminal of a first high-side switch is coupled to a common voltage. A first terminal of a first low-side switch is connected to a second terminal of the first high-side switch. A second terminal of the first low-side switch is grounded. A first terminal of a second low-side switch is connected to a node between the second terminal of the first high-side switch and the first terminal of the first low-side switch. A second terminal of the second low-side switch is grounded. A safe operating area of the second low-side switch is larger than a safe operating area of the first low-side switch. After the first low-side switch is turned off, the second low-side switch is turned off Before the first low-side switch is turned on, the second low-side switch is turned on.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.

Abstract: The invention relates to a method of overcoming immune suppression in tumor microenvironment or stimulating immune response against cancer, comprising administering to a subject a combination of a histone deacetylase (HDAC) inhibitor and a tyrosine kinase inhibitor (TKI).

Abstract: A key structure includes a base plate, a key cap, a positioning base, a positioning cover, and a spring. The key cap is disposed above the base plate and has a bottom surface. The positioning base is connected to the bottom surface of the key cap and has a positioning recess. The positioning cover is slidably connected to the positioning base, is inserted into the positioning recess, and includes a bottom portion and a side wall. The spring includes a first spring portion and a second spring portion. The first spring portion is located in the positioning recess and is in contact with the bottom surface of the key cap. The second spring portion is located in the positioning cover. An orthographic projection of the first spring portion on the bottom surface of the key cap is overlapped with an orthographic projection of the side wall of the positioning cover on the bottom surface of the key cap.

Abstract: A light-emitting device is provided. The light-emitting device includes a light-emitting diode, a reflective structure, and a package structure. The reflective structure includes a bottom surface and a lateral part. The light-emitting diode is disposed on the bottom surface. The lateral part is disposed surrounding the bottom surface and disposed on the bottom surface. The package structure is configured to package the light-emitting diode and the reflective structure. The package structure includes a first package part and a second package part. The first package part has a phosphorescent powder. An interface is between the first package part and the second package part. The interface is disposed below a top surface of the lateral part.

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: A latch mechanism includes a bracket, a sliding element slidably located on the bracket, a latch portion fixedly connected to the sliding element, an elastic element connected to the bracket and the sliding element, and a trigger element including an elongated frame, a through hole and a pressed portion. The elongated frame is slidably located on the bracket, the through hole is formed on one surface of the elongated frame, and the pressed portion is disposed on the one surface of the elongated frame, and directly pressed by the latch portion. When the trigger element is pushed until the through hole is moved to the latch portion, the first elastic element moves the latch portion to extend into the through hole.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Abstract: Example embodiments described herein involve a system for testing a light-emitting module. The light-emitting module may include a mounting platform configured to hold a light-emitting module for a camera. The mounting platform may also be configured to rotate. The system may further include a housing holding a plurality of photodiodes arranged in an array over at least a 90 degree arc of a hemisphere. The system may also include a controller configured to control the photodiodes and the rotation of the mounting platform.

Abstract: A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (b) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.