Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.

Abstract: A plurality of holes in a top surface of a silicon medium form a plurality of sub-meta lenses to result in multiple focal points rather than a single point (resulting from using a single meta lens). As a result, optical paths for incoming light are reduced as compared with a single optical path associated with a single meta lens, which in turn reduces angular response of incident photons. Thus, a pixel sensor including the plurality of sub-meta lenses experiences improved light focus and greater signal-to-noise ratio. Additionally, dimensions of the pixel sensor are reduced (particularly a height of the pixel sensor), which allows for greater miniaturization of an image sensor that includes the pixel sensor.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: Various embodiments of the present application are directed towards an image sensor including a wavelength tunable narrow band filter, as well as methods for forming the image sensor. In some embodiments, the image sensor includes a substrate, a first photodetector, a second photodetector, and a filter. The first and second photodetectors neighbor in the substrate. The filter overlies the first and second photodetectors and includes a first distributed Bragg reflector (DBR), a second DBR, and a first interlayer between the first and second DBRs. A thickness of the first interlayer has a first thickness value overlying the first photodetector and a second thickness value overlying the second photodetector. In some embodiments, the filter is limited to a single interlayer. In other embodiments the filter further includes a second interlayer defining columnar structures embedded in the first interlayer and having a different refractive index than the first interlayer.

Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.

Abstract: A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

Abstract: A system includes at least one server and a power supply having multiple power supply units. After system boot-up, all power supply units in the power supply are turned on for supplying power to the at least one server. Next, the maximum output power value of the power supply and the conversion efficiency table containing the relationship between the loading rate and the conversion efficiency of the power supply are acquired, and the real-time conversion efficiency of the power supply is calculated. When it is determined based on the real-time conversion efficiency and the conversion efficiency table of the power supply that the power supply is not currently operating with an optimized conversion efficiency, one or more power supply units in the power supply are turned off or turned on according to a predetermined rule.

Abstract: An electronic device is provided. The electronic device includes a display panel and a controller coupled to the display panel. The display panel is configured to update displayed images at a refresh rate. The controller is configured to receive a target frame rate from a first application. The controller is further configured to determine a frame rate according to the refresh rate and the target frame rate. The frame rate is a factor of the refresh rate. The controller is further configured to control the first application to draw images at the frame rate.

Abstract: An antenna structure is disposed on a metal unit and includes a first slot, a second slot, and a short-circuiting portion. The first slot is formed on the metal unit. The second slot is formed on the metal unit and located at one side of the first slot. The second slot is configured to receive a signal feed. The short-circuiting portion is in a floating state and extends across the first slot without being in direct contact with the first slot.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A method to form an inductor, the method comprising: forming a metal structure by removing unwanted portions of the metal plate to form a first electrode, a second electrode, and a bare conductor wire between the first electrode and the second electrode, wherein a first thickness of the first electrode is greater than a thickness of the bare conductor wire, and a second thickness of the second electrode is greater than said thickness of the bare conductor wire; and forming a magnetic body to encapsulate the bare conductor wire, and a least one portion of the first electrode and a least one portion of the second electrode.

Abstract: A method to form an inductor, the method comprising: forming a metal structure by removing unwanted portions of the metal plate to form a first electrode, a second electrode, and a bare conductor wire between the first electrode and the second electrode, wherein a first thickness of the first electrode is greater than a thickness of the bare conductor wire, and a second thickness of the second electrode is greater than said thickness of the bare conductor wire; and forming a magnetic body to encapsulate the bare conductor wire, and a least one portion of the first electrode and a least one portion of the second electrode.

Abstract: An inductive component is disclosed, the inductive component comprising a metal structure, comprising a bare conductor wire, a first electrode and a second electrode, wherein the first electrode and the second electrode are integrally formed with the bare conductor wire, wherein a first thickness of the first electrode is greater than that of the bare conductor wire and a second thickness of the second electrode is greater than that of the bare conductor wire; and a magnetic body encapsulating the bare conductor wire, at least one portion of the first electrode, and at least one portion of the second electrode, wherein the first lateral surface of the first electrode and the second lateral surface of the second electrode are embedded inside the magnetic body.

Abstract: A coupled inductor has two coils made by film or a lithography processes, wherein a first coil is disposed on a top surface of a magnetic sheet and a second coil is disposed on the bottom surface of the magnetic sheet, for controlling the variations of the alignments of the two coils in a smaller range.

Abstract: An inductive component is disclosed, the inductive component comprising a metal structure, comprising a bare conductor wire, a first electrode and a second electrode, wherein the first electrode and the second electrode are integrally formed with the bare conductor wire, wherein a first thickness of the first electrode is greater than that of the bare conductor wire and a second thickness of the second electrode is greater than that of the bare conductor wire; and a magnetic body encapsulating the bare conductor wire, at least one portion of the first electrode, and at least one portion of the second electrode, wherein the first lateral surface of the first electrode and the second lateral surface of the second electrode are embedded inside the magnetic body.

Abstract: An in-line system for mass production of an organic optoelectronic device is disclosed. The in-line system includes a patterned holder, a first chamber, and a second chamber. The patterned holder is for holding a substrate covered with a first electrode layer and a contact electrode layer, in which the first electrode layer and the contact electrode layer are partially shielded by the patterned holder. The first chamber is for forming an organic layer on portions of the first electrode layer and the contact electrode layer that are not shielded by the patterned holder. The second chamber is aligned with the first chamber and is for forming a second electrode layer on the organic layer.

Abstract: An in-line system for mass production of an organic optoelectronic device is disclosed. The in-line system includes a patterned holder, a first chamber, and a second chamber. The patterned holder is for holding a substrate covered with a first electrode layer and a contact electrode layer, in which the first electrode layer and the contact electrode layer are partially shielded by the patterned holder. The first chamber is for forming an organic layer on portions of the first electrode layer and the contact electrode layer that are not shielded by the patterned holder. The second chamber is aligned with the first chamber and is for forming a second electrode layer on the organic layer.

Abstract: A light emitting material is represented by the following formula (1), the organic EL device employing the material as delayed fluorescence emitting dopant or fluorescence emitting dopant can display good performance like as lower driving voltage and power consumption, especially doping with the host (H1 to H4) and the second host (SH1 to SH4) can increasing efficiency and half-life time. wherein G represents the following formula (2): L, m, n, p, R1 to R4, Ar and X are the same definition as described in the present invention.