Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: A video signal processing device and method thereof are provided in the present application. The video processing device includes a storage and a processor. The storage stores a plurality of brightness mapping relationships. If set brightness corresponding to the brightness mapping relationships does not match the target brightness, the processor selects a first mapping relationship and a second mapping relationship of two pieces of set brightness closing to target brightness from the brightness mapping relationships. A target mapping relationship corresponding to the target brightness is obtained by an interpolation according to the first mapping relationship, the first brightness, the second mapping relationship and the corresponding set brightness. The processor converts nonlinear brightness information of a first video signal into linear brightness information of a second video signal according to the target mapping relationship.

Abstract: A video signal processing device and method thereof are provided in the present application. The video processing device includes a storage and a processor. The storage stores a plurality of brightness mapping relationships. If set brightness corresponding to the brightness mapping relationships does not match the target brightness, the processor selects a first mapping relationship and a second mapping relationship of two pieces of set brightness closing to target brightness from the brightness mapping relationships. A target mapping relationship corresponding to the target brightness is obtained by an interpolation according to the first mapping relationship, the first brightness, the second mapping relationship and the corresponding set brightness. The processor converts nonlinear brightness information of a first video signal into linear brightness information of a second video signal according to the target mapping relationship.

Abstract: A bicomponent tissue and seedling culture bottle includes an upper cover portion having an opening facing downward, and a lower container portion having a closed base and suitable for fitly but detachably connecting to the downward opening of the upper cover portion, characterized in that, a T-shaped air vent consisting of a vertical air passage centered at a top portion of the upper cover and two horizontal air passages symmetrically located at and extending from two opposite sides of the vertical air passage to be communicable with the outside air, so that air or gas produced in the culture bottle during the culture process can escape from the air vent and germs or viruses can be prevented from entering into the culture bottle when the seedlings are matured and/or are transplanted and the survival percent of the bottle cultured seedlings can be raised.