Patents by Inventor Cheng-Heng Kao
Cheng-Heng Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10332861Abstract: The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively provided on the first and second substrates, in which the second component is not in contact with the first component. Then, a joint component is formed between the first and second components by passing a flow of a fluid comprising ions of a conductive material between the first and second components and electrolessly plating the first and second components by the conductive material so that the joint component is electrically connected between the first and second components. The present disclosure also provides related interconnection structures and a fixture for forming a related microchannel structure.Type: GrantFiled: August 22, 2017Date of Patent: June 25, 2019Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Cheng-Heng Kao, Han-Tang Hung, Chun-Hsiang Yang, Yan-Bin Chen
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Publication number: 20180040798Abstract: A structure of a thermoelectric module including at least one substrate, a thermoelectric device and an insulation protection structure is provided. The thermoelectric device is disposed on the substrate. The insulation protection structure surrounds the thermoelectric device. The thermoelectric device includes at least three electrode plates, first type and second type thermoelectric materials and a diffusion barrier structure. First and second electrode plates among the three electrode plates are disposed on the substrate. The first type thermoelectric material is disposed on the first electrode plate. The second type thermoelectric material is disposed on the second electrode plate. A third electrode plate among the three electrode plates is disposed on the first type and second type thermoelectric materials. The diffusion barrier structure is disposed on two terminals of each of the first type and second type thermoelectric materials.Type: ApplicationFiled: September 30, 2017Publication date: February 8, 2018Applicant: Industrial Technology Research InstituteInventors: Li-Ling Liao, Ming-Ji Dai, Chun-Kai Liu, Cheng-Heng Kao, Cheng-Chieh Li, Jeffrey Snyder, Fivos Drymiotis
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Publication number: 20170373043Abstract: The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively provided on the first and second substrates, in which the second component is not in contact with the first component. Then, a joint component is formed between the first and second components by passing a flow of a fluid comprising ions of a conductive material between the first and second components and electrolessly plating the first and second components by the conductive material so that the joint component is electrically connected between the first and second components. The present disclosure also provides related interconnection structures and a fixture for forming a related microchannel structure.Type: ApplicationFiled: August 22, 2017Publication date: December 28, 2017Inventors: Cheng-Heng KAO, Han-Tang HUNG, Chun-Hsiang YANG, Yan-Bin CHEN
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Patent number: 9786634Abstract: The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively provided on the first and second substrates, in which the second component is not in contact with the first component. Then, a joint component is formed between the first and second components by passing a flow of a fluid comprising ions of a conductive material between the first and second components and electrolessly plating the first and second components by the conductive material so that the joint component is electrically connected between the first and second components. The present disclosure also provides related interconnection structures and a fixture for forming a related microchannel structure.Type: GrantFiled: July 17, 2015Date of Patent: October 10, 2017Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Cheng-Heng Kao, Han-Tang Hung, Chun-Hsiang Yang, Yan-Bin Chen
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Patent number: 9666441Abstract: A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved.Type: GrantFiled: September 14, 2015Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Heng Kao, Samuel C. Pan, Chi-Wen Liu, Miin-Jang Chen, Po-Shuan Yang
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Publication number: 20170018532Abstract: The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively provided on the first and second substrates, in which the second component is not in contact with the first component. Then, a joint component is formed between the first and second components by passing a flow of a fluid comprising ions of a conductive material between the first and second components and electrolessly plating the first and second components by the conductive material so that the joint component is electrically connected between the first and second components. The present disclosure also provides related interconnection structures and a fixture for forming a related microchannel structure.Type: ApplicationFiled: July 17, 2015Publication date: January 19, 2017Inventors: Cheng-Heng KAO, Han-Tang HUNG, Chun-Hsiang YANG, Yan-Bin CHEN
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Publication number: 20170018435Abstract: A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved.Type: ApplicationFiled: September 14, 2015Publication date: January 19, 2017Inventors: Cheng-Heng Kao, Samuel C. Pan, Chi-Wen Liu, Miin-Jang Chen, Po-Shuan Yang
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Publication number: 20160163950Abstract: A structure of a thermoelectric module including at least one substrate, a thermoelectric device and an insulation protection structure is provided. The thermoelectric device is disposed on the substrate. The insulation protection structure surrounds the thermoelectric device. The thermoelectric device includes at least three electrode plates, first type and second type thermoelectric materials and a diffusion barrier structure. First and second electrode plates among the three electrode plates are disposed on the substrate. The first type thermoelectric material is disposed on the first electrode plate. The second type thermoelectric material is disposed on the second electrode plate. A third electrode plate among the three electrode plates is disposed on the first type and second type thermoelectric materials. The diffusion barrier structure is disposed on two terminals of each of the first type and second type thermoelectric materials.Type: ApplicationFiled: December 8, 2014Publication date: June 9, 2016Inventors: Li-Ling Liao, Ming-Ji Dai, Chun-Kai Liu, Cheng-Heng Kao, Cheng-Chieh Li, Jeffrey Snyder, Fivos Drymiotis
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Publication number: 20050127147Abstract: A method for controlling the bond microstructures is disclosed. A Sn layer and an Au layer are sequentially formed on the two members that are to be jointed. The weight ratio of Sn/Au is 20:80 having a variation range about ±3-4%. Next, the Sn layer and the Au layer are treated with a first temperature or a second temperature so that the Sn layer and the Au layer react to form a bond microstructure connecting two members. When the Sn layer and the Au layer are treated with the first temperature, the bond microstructure will have a layered structure. When the Sn layer and the Au layer are treated with the second temperature, the bond microstructure will have an eutectic structure. Therefore, the bond microstructures can be manufactured with a diferent of characteristics by treating with a different of temperatures for suiting various industrial applications.Type: ApplicationFiled: March 7, 2004Publication date: June 16, 2005Inventors: CHENG-HENG KAO, JUI-YUN TSAI, CHIEN-WEI CHANG
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Publication number: 20050104215Abstract: A contact structure is suitable for contacting with a soldering bump. The contact structure mainly comprises a bonding pad and an under bump metallurgy including a platinum barrier layer. The platinum barrier layer is disposed between the bonding pad and the soldering bump. The platinum barrier layer with the lower consumption rate and oxidation resistance capability can be used instead of the conventional nickel barrier layer.Type: ApplicationFiled: June 15, 2004Publication date: May 19, 2005Inventors: Cheng-Heng Kao, Wan-Chun Chang
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Patent number: 6744142Abstract: In a process of fabricating flip chip interconnection, a UBM layer is deposited on an I/O pad of a chip. The UBM layer includes a nickel layer. On the UBM layer is formed a tin-containing solder material. The chip is mounted on a carrier substrate by alignment of the bonding pad with a contact pad of the carrier substrate. A reflow process is performed to respectively turn the tin-containing solder material to a tin-containing solder bump and form a composite intermetallic compound on the nickel layer of the UBM to prevent its spalling.Type: GrantFiled: March 7, 2003Date of Patent: June 1, 2004Assignee: National Central UniversityInventors: Cheng-Yi Liu, Shen-Jie Wang, Cheng-Heng Kao
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Publication number: 20030234453Abstract: In a process of fabricating flip chip interconnection, a UBM layer is deposited on an I/O pad of a chip. The UBM layer includes a nickel layer. On the UBM layer is formed a tin-containing solder material. The chip is mounted on a carrier substrate by alignment of the bonding pad with a contact pad of the carrier substrate. A reflow process is performed to respectively turn the tin-containing solder material to a tin-containing solder bump and form a composite intermetallic compound on the nickel layer of the UBM to prevent its spalling.Type: ApplicationFiled: March 7, 2003Publication date: December 25, 2003Inventors: Cheng-Yi Liu, Shen-Jie Wang, Cheng-Heng Kao
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Publication number: 20030219623Abstract: A solder joint structure comprises a solder of a Sn alloy especially having Cu element contained therein, a contact region having a Ni layer been composed therein. In which, by means of controlling the Cu concentration to select an interface reaction product for reducing the consumption rate of the Ni layer of the contact region so as to provide an durable strength therefore.Type: ApplicationFiled: April 16, 2003Publication date: November 27, 2003Inventors: Cheng Heng Kao, Cheng En Ho, L. C. Shiau
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Patent number: 6642079Abstract: In a process of fabricating flip chip interconnection, a UBM layer is deposited on an I/O pad of a chip. The UBM layer includes a nickel layer. On the UBM layer is formed a tin-containing solder material. The chip is mounted on a carrier substrate by alignment of the bonding pad with a contact pad of the carrier substrate. A reflow process is performed to respectively turn the tin-containing solder material to a tin-containing solder bump and form a composite intermetallic compound on the nickel layer of the UBM to prevent its spalling.Type: GrantFiled: October 1, 2002Date of Patent: November 4, 2003Assignee: National Central UniversityInventors: Cheng-Yi Liu, Shen-Jie Wang, Cheng-Heng Kao
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Patent number: 6602777Abstract: The present invention relates to a method for controlling the formation of the intermetallic compounds in solder joints, The types of the intermetallic compounds between the SnAgCu solders and the Ni-bearing substrate can be controlled by adjusting the copper concentration in the SnAgCu solders. If the SnAgCu solder has a copper concentration higher than or equivalent to 0.6 wt. %, the soldering intermetallic compound includes a continuous (Cu1−xNix)6Sn5 layer. If the copper concentration of the SnAgCu solders is lower than or equivalent to 0.4 wt. %, the soldering intermetallic compound includes a continuous (Ni1−yCuy)3Sn4 layer and a non-continuous (Cu1−xNix)6Sn5 layer. If the copper concentration of the SnAgCu solders is between 0.4 wt. % to 0.6 wt. %, the soldering intermetallic compound includes the continuous (Cu1−xNix)6Sn5.Type: GrantFiled: March 20, 2002Date of Patent: August 5, 2003Assignee: National Central UniversityInventors: Cheng-Heng Kao, Cheng-En Ho
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Publication number: 20030132271Abstract: The present invention relates to a method for controlling the formation of the intermetallic compounds in solder joints, The types of the intermetallic compounds between the SnAgCu solders and the Ni-bearing substrate can be controlled by adjusting the copper concentration in the SnAgCu solders. If the SnAgCu solder has a copper concentration higher than or equivalent to 0.6 wt. %, the soldering intermetallic compound includes a continuous (Cu1−xNix)6Sn5 layer. If the copper concentration of the SnAgCu solders is lower than or equivalent to 0.4 wt. %, the soldering intermetallic compound includes a continues (Ni1−yCuy)3Sn4 layer and a non-continuous (Cu1−xNix)6Sn5 layer. If the copper concentration of the SnAgCu solders is between 0.4 wt. % to 0.6 wt.Type: ApplicationFiled: March 20, 2002Publication date: July 17, 2003Inventors: Cheng-Heng Kao, Cheng-En Ho