Patents by Inventor Cheng-Hong Tsai
Cheng-Hong Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12387023Abstract: Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.Type: GrantFiled: June 1, 2022Date of Patent: August 12, 2025Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Huei Li, Cheng-Hong Tsai, Chien-Cheng Wu, Yen-Chih Chiu, Hu-Cheng Jiang
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Publication number: 20230342529Abstract: Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.Type: ApplicationFiled: June 1, 2022Publication date: October 26, 2023Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Huei Li, Cheng-Hong Tsai, Chien-Cheng Wu, Yen-Chih Chiu, Hu-Cheng Jiang
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Patent number: 10503857Abstract: A computer executing method is provided in this disclosure. The computer executing method is configured for synthesizing a clock tree circuit, the clock tree circuit includes a plurality of clock pins, a plurality of weight values are set between any of the clock pins, the computer executing method includes steps of: establishing a graph model; utilizing a force directed algorithm to calculate a branch position according to the weight values and a position of the clock pins; setting a guide buffer in the branch position and updating a netlist; performing a clock tree synthesis (CTS) and executing a post-CTS static timing analysis (STA); determining whether an analysis result of the post-CTS STA and a timing setup value is identical or not; and if the analysis result does not match the timing setup value, re-establishing a graph model.Type: GrantFiled: April 19, 2018Date of Patent: December 10, 2019Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yih-Chih Chou, Cheng-Hong Tsai, Chih-Mou Tseng
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Publication number: 20190251211Abstract: A computer executing method is provided in this disclosure. The computer executing method is configured for synthesizing a clock tree circuit, the clock tree circuit includes a plurality of clock pins, a plurality of weight values are set between any of the clock pins, the computer executing method includes steps of: establishing a graph model; utilizing a force directed algorithm to calculate a branch position according to the weight values and a position of the clock pins; setting a guide buffer in the branch position and updating a netlist; performing a clock tree synthesis (CTS) and executing a post-CTS static timing analysis (STA); determining whether an analysis result of the post-CTS STA and a timing setup value is identical or not; and if the analysis result does not match the timing setup value, re-establishing a graph model.Type: ApplicationFiled: April 19, 2018Publication date: August 15, 2019Inventors: Yih-Chih CHOU, Cheng-Hong TSAI, Chih-Mou TSENG
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Patent number: 9710580Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.Type: GrantFiled: July 6, 2015Date of Patent: July 18, 2017Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Teng-Nan Liao, Te-Hsun Fu, Hsin-Hsiung Liao, Cheng-Hong Tsai, Min-Hsiu Tsai
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Publication number: 20170011161Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.Type: ApplicationFiled: July 6, 2015Publication date: January 12, 2017Inventors: Teng-Nan Liao, Te-Hsun Fu, Hsin-Hsiung Liao, Cheng-Hong Tsai, Min-Hsiu Tsai
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Patent number: 8453090Abstract: In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition.Type: GrantFiled: October 21, 2010Date of Patent: May 28, 2013Assignee: Global Unichip Corp.Inventor: Cheng-Hong Tsai
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Publication number: 20120102447Abstract: In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition.Type: ApplicationFiled: October 21, 2010Publication date: April 26, 2012Applicant: Global Unichip Corp.Inventor: Cheng-Hong Tsai
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Publication number: 20060139285Abstract: An overdrive system is disposed on a computer motherboard and generates an overdriven signal through an overdrive chip. By using a preset lookup table database in the overdrive chip, the overdrive chip optimizes image signals according to different liquid crystal display (LCD) panels to accommodate the character of each LCD panel.Type: ApplicationFiled: December 23, 2005Publication date: June 29, 2006Applicant: BENQ CORPORATIONInventor: Cheng-Hong Tsai
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Publication number: 20060044218Abstract: A display device including a graphic unit, a memory, a video enhancing unit and a display monitor is provided. The graphic unit is for outputting a first video. The memory stores a number of predetermined parameter. The video enhancing unit, which receives the first video and selects a enhancing control parameter from a number of predetermined parameters, adjusts the first video, then outputs a second video. Lastly, the display monitor displays an image according to second video.Type: ApplicationFiled: August 26, 2005Publication date: March 2, 2006Inventors: Cheng-Hong Tsai, Yu-Chih Liu