Abstract: A memory device including a substrate, a plurality of stack structures, and a protective layer is provided. The plurality of stack structures are arranged along a first direction on an array area of the substrate, and each of the stack structures extends along a second direction different from the first direction. In a cross-sectional view of the memory device, each of the stack structures includes, in sequence from the substrate, a charge storage structure, a control gate, and a cap layer. The cap layer has a multilayer structure. The protective layer covers sidewalls of the stack structures. A width in the first direction of the charge storage structure, a width of the control gate, and a width of the cap layer are substantially equal to each other.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate with a word line region and a select gate region adjacent to each other, sequentially forming a stack layer and a hard mask layer on the substrate, and forming patterned mandrels on the hard mask layer. The method includes forming sidewall spacers on the patterned mandrels, and forming a patterned photoresist over the select gate region. The method further includes sequentially patterning the hard mask layer and the stack layer to form word lines in the word line region and a select gate in the select gate region, respectively. There is a first spacing between the word lines, and a second spacing between the select gate and the first word line of the word lines closest to the select gate. The second spacing is greater than the first spacing.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformally formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: A method for forming a semiconductor structure includes: forming an active layer on a substrate; forming hard masks on the active layer, wherein a first spacing is disposed between two closely spaced hard masks in a predetermined word line region nearest to a predetermined selective gate region, wherein the first spacing is less than a second spacing between any two of the hard masks other than the two closely spaced hard masks; forming spacers on the sidewalls of the hard masks, wherein two spacers on opposite sides of the sidewalls of the closely spaced hard masks merge into a combined spacer; and transferring the patterns of the spacers to the active layer to form word lines. The step of transferring the patterns of the spacers includes transferring the pattern of the combined spacer to the active layer to form a first word line.

Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformally formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: A memory device including a substrate, a plurality of stack structures, and a protective layer is provided. The plurality of stack structures are arranged along a first direction on an array area of the substrate, and each of the stack structures extends along a second direction different from the first direction. In a cross-sectional view of the memory device, each of the stack structures includes, in sequence from the substrate, a charge storage structure, a control gate, and a cap layer. The cap layer has a multilayer structure. The protective layer covers sidewalls of the stack structures. A width in the first direction of the charge storage structure, a width of the control gate, and a width of the cap layer are substantially equal to each other.

Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformity formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.

Abstract: A semiconductor structure includes a trunk portion and a branch portion. The trunk portion extends in a first direction. The branch portion is connected to the trunk portion. The branch portion includes a handle portion and a two-pronged portion. The handle portion is connected to the trunk portion and extends in a second direction. The second direction intersects the first direction. The two-pronged portion is connected to the handle portion. A line width of the handle portion is greater than a line width of the two-pronged portion.

Abstract: A semiconductor structure includes a trunk portion and a branch portion. The trunk portion extends in a first direction. The branch portion is connected to the trunk portion. The branch portion includes a handle portion and a two-pronged portion. The handle portion is connected to the trunk portion and extends in a second direction. The second direction intersects the first direction. The two-pronged portion is connected to the handle portion. A line width of the handle portion is greater than a line width of the two-pronged portion.

Abstract: A method for forming a semiconductor structure includes: forming an active layer on a substrate; forming hard masks on the active layer, wherein a first spacing is disposed between two closely spaced hard masks in a predetermined word line region nearest to a predetermined selective gate region, wherein the first spacing is less than a second spacing between any two of the hard masks other than the two closely spaced hard masks; forming spacers on the sidewalls of the hard masks, wherein two spacers on opposite sides of the sidewalls of the closely spaced hard masks merge into a combined spacer; and transferring the patterns of the spacers to the active layer to form word lines. The step of transferring the patterns of the spacers includes transferring the pattern of the combined spacer to the active layer to form a first word line.

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformity formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: A manufacturing method of a semiconductor chip is provided. The method includes: forming a first metal pattern over a substrate and within a chip region and a scribe line region of the substrate, wherein the chip region is surrounded by the scribe line region; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all portions of the metal material layer within the scribe line region and a portion of the metal material layer within the chip region, so as to form a second metal pattern within the chip region; forming a third metal pattern, wherein the second metal pattern within the chip region is covered by the third metal pattern, and the third metal pattern is located over the first metal pattern within the scribe line region; and performing singulation along the scribe line region, to form the semiconductor chip.

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.

Abstract: A method of wafer dicing and a die are provided. The method includes the following processes. A wafer is provided, the wafer includes a plurality of die regions and a scribe region between the die regions. The scribe region includes a substrate, and a dielectric layer and a test structure on the substrate, the test structure is disposed in the dielectric layer. A first removal process is performed to remove the test structure and the dielectric layer around the test structure, so as to expose the substrate. The first removal process includes performing a plurality of etching cycles, and each etching cycle includes performing a first etching process to remove a portion of the test structure and performing a second etching process to remove a portion of the dielectric layer. A second removal process is performed to remove the substrate in the scribe region, so as to form a plurality of dies separated from each other.

Abstract: A manufacturing method of a semiconductor chip is provided. The method includes: forming a first metal pattern over a substrate and within a chip region and a scribe line region of the substrate, wherein the chip region is surrounded by the scribe line region; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all portions of the metal material layer within the scribe line region and a portion of the metal material layer within the chip region, so as to form a second metal pattern within the chip region; forming a third metal pattern, wherein the second metal pattern within the chip region is covered by the third metal pattern, and the third metal pattern is located over the first metal pattern within the scribe line region; and performing singulation along the scribe line region, to form the semiconductor chip.