Patents by Inventor Cheng Hsiang

Cheng Hsiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176143
    Abstract: A head-mounted display, controlling method, and non-transitory computer readable storage medium thereof are provided. The head-mounted display determines a first posture among a plurality of postures based on a plurality of real-time images. The head-mounted display generates a first gesture among a plurality of gestures corresponding to a user according to a plurality of inertial measurement parameters corresponding to a first body part of the user. The head-mounted display generates a control signal corresponding to a first output event among a plurality of output events based on the first gesture and the first gesture.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Chao-Hsiang Lai, Cheng-Han Hsieh, Tzu-Wei Huang
  • Publication number: 20240171160
    Abstract: A sensing circuit coupled to a sensor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an oscillator. The first transistor, coupled to a first current source and the sensor, receives a sensing current from the sensor. A gate terminal of the first transistor is connected to a source terminal of the first transistor. The second transistor, coupled to the first transistor and a second current source, generates a first current according to the sensing current. The first current is greater than the sensing current. The third transistor, coupled to the second transistor and the second current source, generates a second current according to the first current. The fourth transistor, coupled to the third transistor, generates a third current. The oscillator is coupled to the fourth transistor. The oscillator generates a signal having an oscillation frequency according to the third current.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Tsun Chen, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20240172273
    Abstract: Examples pertaining to preamble puncturing negotiation in wireless communications are described. A station (STA) may receive a control frame, and, in response, apply the MRU pattern for one or more transmissions or receptions in a transmission opportunity (TXOP). In the control frame, either a plurality of first reserved bits in a SERVICE field or a plurality of bits in a User Info field are set to indicate a multiple resource unit (MRU) pattern regarding preamble puncturing.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: Cheng-Yi Chang, Kun-Sheng Huang, Yi-Hsuan Chung, Chung-Kai Hsu, Chia-Hsiang Chang, Kai Ying Lu
  • Publication number: 20240170385
    Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 23, 2024
    Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Mei-Yen CHEN, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
  • Patent number: 11990291
    Abstract: A multiple function button for an information handling system includes an outer shell and an inner button. The outer shell includes multiple channels having first, second, third and fourth channels. The inner button is inserted within the outer shell. The inner button includes a tab and a contact component. The tab moves within the multiple channels. When the tab is within the first channel, the inner button is in a first position and contact component is positioned over a first contact of the information handling system. When the tab is within the third channel, the inner button is in a second position and the contact component is positioned over a second contact of the information handling system.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: May 21, 2024
    Assignee: Dell Products L.P.
    Inventors: Jer-Yo Lee, Chun-Ting Lu, Cheng-Hsiang Chuang
  • Patent number: 11988625
    Abstract: A capacitive biosensor is provided. The capacitive biosensor includes: a transistor, an interconnect structure on the transistor, and a passivation layer on the interconnect structure. The interconnect structure includes a first metal structure on the transistor, a second metal structure on the first metal structure, and a third metal structure on the second metal structure. The third metal structure includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked. The passivation has an opening exposing a portion of the third metal structure. The capacitive biosensor further includes a sensing region on the interconnect structure. The sensing region includes a first sensing electrode and a second sensing electrode. The first sensing electrode is formed of the third conductive layer, and the second sensing electrode is disposed on the passivation layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 21, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Ping Chang, Chien-Hui Li, Chien-Hsun Wu, Tai-I Yang, Yung-Hsiang Chen
  • Publication number: 20240160919
    Abstract: In aspects of the disclosure, a method, a system, and a computer-readable medium are provided. The method of building a kernel reparameterization for replacing a convolution-wise operation kernel in training of a neural network comprises selecting one or more blocks from tensor blocks and operations; and connecting the selected one or more blocks with the selected operations to build the kernel reparameterization. The kernel reparameterization has a dimension same as that of the convolution-wise operation kernel.
    Type: Application
    Filed: October 17, 2023
    Publication date: May 16, 2024
    Inventors: Po-Hsiang Yu, Hao Chen, Peng-Wen Chen, Cheng-Yu Yang
  • Publication number: 20240160928
    Abstract: A method for enhancing kernel reparameterization of a non-linear machine learning model includes providing a predefined machine learning model, expanding a kernel of the predefined machine learning model with a non-linear network for convolution operation of the predefined machine learning model to generate the non-linear machine learning model, training the non-linear machine learning model, reparameterizing the non-linear network back to a kernel for convolution operation of the non-linear machine learning model to generate a reparameterized machine learning model, and deploying the reparameterized machine learning model to an edge device.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Po-Hsiang Yu, Hao Chen, Cheng-Yu Yang, Peng-Wen Chen
  • Publication number: 20240161013
    Abstract: A reparameterization method for initializing a machine learning model includes initializing a prefix layer of a first low dimensional layer in the machine learning model and a postfix layer of the first low dimensional layer, inverting the prefix layer to generate an inverse prefix layer of the first low dimensional layer, inverting the postfix layer to generate an inverse postfix layer of the first low dimensional layer, combining the inverse prefix layer, the first low dimensional layer and the inverse postfix layer to form a high dimensional layer, generating parallel operation layers from the high dimensional layer, and assigning initial weights to the parallel operation layers.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Cheng-Yu Yang, Hao Chen, Po-Hsiang Yu, Peng-Wen Chen
  • Patent number: 11978768
    Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: May 7, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Tseng-Yao Pan, Chien-Hsiang Yu, Ching-Yung Wang, Cheng-Hong Wei, Ming-Tsang Wang
  • Publication number: 20240145370
    Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.
    Type: Application
    Filed: December 18, 2022
    Publication date: May 2, 2024
    Applicant: InnoLux Corporation
    Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
  • Publication number: 20240147658
    Abstract: A fan module and computing device with the fan module are disclosed. The fan module includes a handle configured to actuate between an operation state and a release state. The handle in the release state allows a user to vertically remove the fan module from its respective fan module slot and away from the bottom panel.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 2, 2024
    Inventors: Chao-Jung CHEN, Chih-Hsiang LEE, Wei-Pin CHEN, Jyue HOU, Cheng-Chieh WENG
  • Patent number: 11972951
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Publication number: 20240135184
    Abstract: Aspects of the disclosure provide an evolutionary neural architecture search (ENAS) method. For example, the ENAS method can include steps (a) performing one or more evolutionary operations on an initial population of neural architectures to generate offspring neural architectures, (b) evaluating performance of each of the offspring neural architectures to obtain at least one evaluation value of the offspring neural architecture with respect to a performance metric, (c) adjusting the evaluation values of the offspring neural architectures based on at least one constraint on the evaluation values, (d) selecting at least one of the offspring neural architectures as a new population of neural architectures, and (e) outputting the new population of neural architectures as a last population of neural architectures when a stopping criterion is achieved, or (f) iterating steps (a) to (d) with the new population of neural architectures being taken as the initial population of neural architectures.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yun-Chan TSAI, Min-Fong HORNG, Chia-Hsiang LIU, Cheng-Sheng CHAN, ShengJe HUNG
  • Patent number: 11965898
    Abstract: An automatic nucleic acid detection system and a method thereof are disclosed. The automatic nucleic acid detection method includes: performing, by an automatic control subsystem, on a nucleic acid extraction machine platform, a nucleic acid extraction on one or more specimens in a sample tray to generate one or more corresponding nucleic acids in the sample tray; distributing, by the automatic control subsystem, on a nucleic acid distribution machine platform, the nucleic acid in each hole of the sample tray and a first reagent into a plurality of holes of a detection tray, wherein the number of holes of the detection tray is greater than that of the sample tray; and performing, by the automatic control subsystem, on a nucleic acid detection machine platform, a nucleic acid detection on the detection tray.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 23, 2024
    Assignees: TCI GENE INC, TCI CO., LTD
    Inventors: Yung-Hsiang Lin, Cheng-Hong Hsieh, Ciao-Ting Chen, Tsung-Cheng Chen
  • Patent number: 11968293
    Abstract: Context information of a handshake between a source entity and a target entity is obtained at a security proxy. The context information is transmitted from the security proxy to a key manager. The key manager maintains a first private key of the security proxy. A first handshake message is received from the key manager. The first handshake message is generated at least based on the context information and signed with the first private key. The first handshake message is then transmitted to the target entity.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Wei-Hsiang Hsiung, Chun-Shuo Lin, Wei-Jie Liau, Cheng-Ta Lee
  • Publication number: 20240126559
    Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.
    Type: Application
    Filed: March 15, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chi HUANG, Shu-Cheng CHOU, Yu-Hsiang LIN
  • Publication number: 20240128689
    Abstract: An electrical connection assembly includes two electrical connectors and a bridge connector. Each of the two electrical connectors includes plural terminals and an insulation housing that accommodates the terminals. The bridge connector is located between the two electrical connectors. The bridge connector includes an insulation body, a conductive plastic, plural signal terminals, and plural ground terminals. The conductive plastic is covered by the insulation body. The ground terminals and the signal terminals of the bridge connector are arranged at intervals. The ground terminals of the bridge connector are in electrical contact with the conductive plastic. When two opposite sides of the insulation body are respectively coupled to the two electrical connectors so as to be surrounded by the two electrical connectors, the ground terminals of the bridge connector are respectively in electrical contact with the ground terminals of the two electrical connectors.
    Type: Application
    Filed: February 2, 2023
    Publication date: April 18, 2024
    Inventors: Kuo Hua HUANG, Cheng Hsiang HSUEH, I Chiao TSO
  • Publication number: 20240126006
    Abstract: A backlight module comprises an outer frame unit, a light guide plate arranged in the outer frame unit, a light-emitting unit, a plurality of adhesives for fixing the light-emitting unit on the light guide plate, and a plurality of abutting structures. The light-emitting unit includes a flexible circuit board and a plurality of light-emitting elements arranged on the flexible circuit board at intervals. Part of the flexible circuit board is deformed at a specific position by the abutting structures, and the position of the light-emitting elements relative to the light guide plate can be adjusted. Thereby, the light-emitting elements can be aligned with the light incident surface of the light guide plate, prevent light from leaking from the light emitting surface of the light guide plate close to the light-emitting elements, and reduce the generation of bright lines and improving the overall uniformity. The present invention also provides a display device including the backlight module.
    Type: Application
    Filed: September 14, 2023
    Publication date: April 18, 2024
    Applicant: Radiant Opto-Electronics Corporation
    Inventors: Chih-Hsiang CHEN, Cheng-Te CHANG
  • Publication number: 20240129632
    Abstract: A wafer position status inspection apparatus includes a wafer transportation device, a robotic arm rotatably mounted on the wafer transportation device, an image capture device arranged on the robotic arm, a light flashing device arranged at one side of the image capture device, and a status inspection section in information connection with the image capture device. An image capturing direction of the image capture device is set consistent with a gripping direction of the robotic arm, and a light projecting direction of the light flashing device is consistent with the image capturing direction. The light flashing device projects light on a wafer to generate a light-reflecting contour, which is captured by the image capture device to form a wafer contour image based on which the status inspection section acquires a wafer deposition status to identify various wafer statuses including incline, overlap, absence, and warp.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 18, 2024
    Inventors: Yu-Hsin Liu, Cheng-Hsiang Lu, Daisuke Sasaki