Abstract: The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which prevents the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

Abstract: The present disclosure provides a semiconductor memory structure, including a substrate, a gate structure, a first shallow trench isolation (STI), and a second STI. The gate structure, the first STI, and a second STI are disposed in the substrate. The gate structure is buried in the substrate. The gate structure is disposed between the first STI and the second STI.

Abstract: A method for preparing a semiconductor device structure includes forming a nitrogen-containing pattern over a semiconductor substrate. The method also includes performing an energy treating process to form a transformed portion in the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate such that the transformed portion is surrounded by an opening structure.

Abstract: A method for preparing a semiconductor device structure includes forming a nitrogen-containing pattern over a semiconductor substrate. The method also includes performing an energy treating process to form a transformed portion in the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate such that the transformed portion is surrounded by an opening structure.

Abstract: The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

Abstract: The present disclosure provides a semiconductor memory structure, including a substrate, a gate structure, a first shallow trench isolation (STI), and a second STI. The gate structure, the first STI, and a second STI are disposed in the substrate. The gate structure is buried in the substrate. The gate structure is disposed between the first STI and the second STI.

Abstract: The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which prevents the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

Abstract: The present disclosure provides a semiconductor device with an air gap for reducing parasitic capacitance between conductive features. The semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate; a bit line structure disposed over and electrically connected to the first source/drain region; a capacitor contact disposed over and electrically connected to the second source/drain region; a first spacer structure sandwiched between the bit line structure and the capacitor contact, wherein the first spacer structure comprises an air gap; and a second spacer structure disposed over the first spacer structure, wherein the air gap is covered by the second spacer structure.

Abstract: The present disclosure provides a semiconductor memory structure, including a substrate, a gate structure, a first shallow trench isolation (STI), and a second STI. The gate structure, the first STI, and a second STI are disposed in the substrate. The gate structure is buried in the substrate. The gate structure is disposed between the first STI and the second STI.

Abstract: A method for preparing a semiconductor device structure includes forming a nitrogen-containing pattern over a semiconductor substrate. The method also includes performing an energy treating process to form a transformed portion in the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate such that the transformed portion is surrounded by an opening structure.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.

Abstract: The present disclosure provides a semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.

Abstract: A method of forming semiconductor structure includes forming a bit line structure on a substrate, forming a first landing pad material lower than the bit line structure between two adjacent bit line structures, shaping a top surface of the bit line structure to form an edge area of the top surface lower than a center area of the top surface, forming a second landing pad material on the bit line structure and the first landing pad material, and removing at least a portion of the second landing pad material to form a landing pad.

Abstract: The present disclosure provides a semiconductor device with an air gap for reducing parasitic capacitance between a bit line and a capacitor contact and a method for forming the semiconductor device. The method includes forming a first source/drain region and a second source/drain region in a semiconductor substrate, and forming a bit line over and electrically connected to the first source/drain region. The method also includes forming a first spacer structure on a sidewall of the bit line, and forming a capacitor contact over and electrically connected to the second source/drain region. The capacitor contact is adjacent to the first spacer structure, and the first spacer structure is etched during the forming the capacitor contact. The method further includes forming a second spacer structure over the etched first spacer structure, and performing a heat treatment process to transform a portion of the first spacer structure into an air gap after the second spacer structure is formed.

Abstract: The present disclosure provides a semiconductor device with an air gap for reducing parasitic capacitance between conductive features. The semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate; a bit line structure disposed over and electrically connected to the first source/drain region; a capacitor contact disposed over and electrically connected to the second source/drain region; a first spacer structure sandwiched between the bit line structure and the capacitor contact, wherein the first spacer structure comprises an air gap; and a second spacer structure disposed over the first spacer structure, wherein the air gap is covered by the second spacer structure.

Abstract: The present disclosure provides a semiconductor device with an air gap for reducing parasitic capacitance between a bit line and a capacitor contact and a method for forming the semiconductor device. The method includes forming a first source/drain region and a second source/drain region in a semiconductor substrate, and forming a bit line over and electrically connected to the first source/drain region. The method also includes forming a first spacer structure on a sidewall of the bit line, and forming a capacitor contact over and electrically connected to the second source/drain region. The capacitor contact is adjacent to the first spacer structure, and the first spacer structure is etched during the forming the capacitor contact. The method further includes forming a second spacer structure over the etched first spacer structure, and performing a heat treatment process to transform a portion of the first spacer structure into an air gap after the second spacer structure is formed.

Abstract: The present disclosure provides a semiconductor device structure with fine patterns at different levels and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns and reduces the parasitic capacitance between fine patterns The semiconductor device structure includes a substrate; a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion, a height of the first portion and a height of the second portion are greater than a height of the third portion; a second target structure disposed over the target layer, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion: a low-level conductive pattern positioned between the first target structure and the second target structure; and a high-level conductive pattern positioned in the first target structure.

Abstract: The present application discloses a semiconductor device with the multi-layered connecting structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a single-layered connecting structure positioned above the substrate, and a multi-layered connecting structure positioned above the substrate and including a plurality of first conductive layers and a plurality of second conductive layers alternatively stacked. A top surface of the multi-layered connecting structure is substantially coplanar with a top surface of the single-layered connecting structure and a width of the multi-layered connecting structure is less than a width of the single-layered connecting structure.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.

Abstract: The present disclosure provides a semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.