Patents by Inventor Cheng-Hsiang Kuo

Cheng-Hsiang Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11947173
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20240105121
    Abstract: An electronic device includes a substrate, a first silicon transistor, a second silicon transistor and a first oxide semiconductor transistor. The first silicon transistor, the second silicon transistor and the first oxide semiconductor transistor are disposed on the substrate. The first silicon transistor has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second silicon transistor has a first terminal electrically connected to the second terminal of the first silicon transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first silicon transistor. The first oxide semiconductor transistor has a first terminal electrically connected to the first terminal of the second silicon transistor. Wherein, a voltage value of the first voltage level is greater than a voltage value of the second voltage level.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Lien-Hsiang CHEN, Kung-Chen KUO, Ming-Chun TSENG, Cheng-Hsu CHOU, Kuan-Feng LEE
  • Patent number: 11929271
    Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Kang Hu, Shou-Wen Kuo, Sheng-Hsiang Chuang, Jiun-Rong Pai, Hsu-Shui Liu
  • Publication number: 20240069277
    Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
  • Patent number: 10757543
    Abstract: A method implemented by a server includes: sending a link short message (LSM) to a terminal; generating a communication token (C token) based on a link request of the terminal, and determining whether the server has stored another identical C token; when negative, storing the C token, and sending web data and the C token to the terminal; when affirmative, further determining whether a web cookie in the link request contains a browsing token identical to the C token; when affirmative, sending the web data to the terminal; and when negative, sending a verification short message (VSM) to the terminal, and sending the web data to the terminal upon receiving a verification request within a predetermined duration since sending the VSM.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 25, 2020
    Assignee: TEAMPLUS TECHNOLOGY INC.
    Inventor: Cheng-Hsiang Kuo
  • Patent number: 10728191
    Abstract: A method for establishing communication includes: in receipt of identification information associated with an outside party from an inside party, transmitting, by a closed server, link information to an outside party device associated with the outside party via a public server; in receipt of a request from the outside party device executing an instant messaging application, transmitting, by the public server, an identifier associated with a communication group to the outside party device; and in receipt of the identifier, adding, by the closed server, the outside party to the communication group and enabling the outside party to communicate exclusively with the inside party via an instant messaging service.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: July 28, 2020
    Assignee: Teamplus Technology Inc.
    Inventor: Cheng-Hsiang Kuo
  • Publication number: 20190297036
    Abstract: A method for establishing communication includes: in receipt of identification information associated with an outside party from an inside party, transmitting, by a closed server, link information to an outside party device associated with the outside party via a public server; in receipt of a request from the outside party device executing an instant messaging application, transmitting, by the public server, an identifier associated with a communication group to the outside party device; and in receipt of the identifier, adding, by the closed server, the outside party to the communication group and enabling the outside party to communicate exclusively with the inside party via an instant messaging service.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 26, 2019
    Inventor: Cheng-Hsiang KUO
  • Patent number: 8079539
    Abstract: A built-in module for an inverter and having tension control with integrated tension and velocity closed loops, where required tension feedbacks can be obtained by internal calculations of the inverter or feedback signals of a tension sensor. The tension control module is applied to provide a tension control for a winding mechanism which is operated by driving at least one motor. The tension control module firstly builds a tension control to provide a balanced tension to the winding mechanism. Afterward, the tension control module builds a velocity control to provide an accelerated or decelerated adjustment for the winding mechanism. Accordingly, the winding mechanism can stably maintain a tension-balanced operation.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: December 20, 2011
    Assignee: Delta Electronics, Inc.
    Inventors: Chien-Ping Huang, Cheng-Hsiang Kuo
  • Publication number: 20110180649
    Abstract: A built-in module for an inverter and having tension control with integrated tension and velocity closed loops, where required tension feedbacks can be obtained by internal calculations of the inverter or feedback signals of a tension sensor. The tension control module is applied to provide a tension control for a winding mechanism which is operated by driving at least one motor. The tension control module firstly builds a tension control to provide a balanced tension to the winding mechanism. Afterward, the tension control module builds a velocity control to provide an accelerated or decelerated adjustment for the winding mechanism. Accordingly, the winding mechanism can stably maintain a tension-balanced operation.
    Type: Application
    Filed: January 26, 2010
    Publication date: July 28, 2011
    Inventors: Chien-Ping HUANG, Cheng-Hsiang Kuo