Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

Abstract: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

Abstract: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

Abstract: The invention is directed to an operating method for an image-sensing unit and the image-sensing device using the same. The image-sensing unit comprises a photogate, a photodiode assembled with the photogate, and a first switch. One terminal of the first switch is coupled to a reference voltage, and the other terminal thereof is coupled to the photodiode. The operating method comprises: (a)Applying a first voltage to the photogate, (b)Turning on a first switch, (c)Turning off the first switch at a first time, (d)The photodiode being irradiated by a light, (e)Stopping applying a first voltage value to the photogate at a second time, (f)Applying a second voltage to the photogate at a third time, and (g)Maintaining the turn-off state of the first switch until a fourth time. The operating method for an image-sensing unit enables the image-sensing device using the same to enhance the dynamic range thereof.

Abstract: An image sensor comprising a pixel sensor, a first transistor, a second transistor, a third transistor and a fourth transistor. The pixel sensor receives illumination to generate a photocurrent. The first transistor coupled to a voltage source and the pixel sensor, is controlled by a reset signal to activate or deactivate. A first node is coupled to the first transistor and the pixel sensor, and the voltage source provide a first potential. The second transistor coupled to a second node and the first node, receives a reference voltage. The third transistor, coupled to the voltage source, is controlled by the voltage on the second node. The fourth transistor coupled to the third transistor and the image sensor, is controlled by a selection signal to activate or deactivate.

Abstract: A digital pixel sensor, comprising a first switch coupled between a first voltage and a first node, turned on or off by a rest signal to provide a first voltage to the first node when turned on; a light sensing unit coupled to the first node generating a transformation current responsive to the intensity of an incident light source and thereby discharging the first node, and a decision device coupled with the first node and a reference signal to output an intensity reference signal corresponding to the intensity of the incident light source when the voltage at the first node is discharged to a level below that of the reference signal.

Abstract: The invention is directed to an operating method for an image-sensing unit and the image-sensing device using the same. The image-sensing unit comprises a photogate, a photodiode assembled with the photogate, and a first switch. One terminal of the first switch is coupled to a reference voltage, and the other terminal thereof is coupled to the photodiode. The operating method comprises: (a)Applying a first voltage to the photogate, (b)Turning on a first switch, (c)Turning off the first switch at a first time, (d)The photodiode being irradiated by a light, (e)Stopping applying a first voltage value to the photogate at a second time, (f)Applying a second voltage to the photogate at a third time, and (g)Maintaining the turn-off state of the first switch until a fourth time. The operating method for an image-sensing unit enables the image-sensing device using the same to enhance the dynamic range thereof.

Abstract: An image sensor comprising a pixel sensor, a first transistor, a second transistor, a third transistor and a fourth transistor. The pixel sensor receives illumination to generate a photocurrent. The first transistor coupled to a voltage source and the pixel sensor, is controlled by a reset signal to activate or deactivate. A first node is coupled to the first transistor and the pixel sensor, and the voltage source provide a first potential. The second transistor coupled to a second node and the first node, receives a reference voltage. The third transistor, coupled to the voltage source, is controlled by the voltage on the second node. The fourth transistor coupled to the third transistor and the image sensor, is controlled by a selection signal to activate or deactivate.

Abstract: A digital pixel sensor, comprising a first switch coupled between a first voltage and a first node, turned on or off by a rest signal to provide a first voltage to the first node when turned on; a light sensing unit coupled to the first node generating a transformation current responsive to the intensity of an incident light source and thereby discharging the first node, and a decision device coupled with the first node and a reference signal to output an intensity reference signal corresponding to the intensity of the incident light source when the voltage at the first node is discharged to a level below that of the reference signal