Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: A fabrication method of a circuit includes drilling holes in a substrate, so as to form a plurality of first opening holes and second opening holes in the substrate. A cover film is attached onto the substrate, so as to cover the first opening holes and the second opening holes. A portion of the cover film covering the first opening holes is removed, so as to expose the first opening holes. The first opening holes are filled.

Abstract: A fabrication method of a circuit includes drilling holes in a substrate, so as to form a plurality of first opening holes and second opening holes in the substrate. A cover film is attached onto the substrate, so as to cover the first opening holes and the second opening holes. A portion of the cover film covering the first opening holes is removed, so as to expose the first opening holes. The first opening holes are filled.

Abstract: A display apparatus includes a multiplexer circuit, a driving unit, a first control line and a second control line. The multiplexer circuit includes a plurality of switch units. The first control line is electrically connected with the switch units and the driving unit. The second control line is electrically connected with the switch units and the driving unit. A maximum time constant from the driving unit to the switch units is less than R*C/4, wherein R represents the equivalent resistance of the portion of the first control line between the two switch units which are the farthest from each other, and C represents the equivalent capacitance of the portion of the first control line between the two switch units which are the farthest from each other.

Abstract: A display device is provided. In the display device, sub-pixels are coupled to scan lines and data lines. On the same scan line, the sub-pixels with a predetermined number are belonged into a pixel group. For two pixel groups coupled to the same data lines and respectively coupled to two adjacent scan lines, two sub-pixels, which are respectively belonged into the two pixel groups and successively receive the corresponding data signals in time, receive the same one of the various color information. For each pixel group, in each display period, the enable states of the clock signals have a plurality of combinations having a specific number, the specific number is 2×CK2, where C represents two clock signals are selected from the clock signal having the predetermined number, and K is a positive integer.

Abstract: A transflective type liquid crystal panel includes a plurality of sub-pixels arranged in rows and columns to form a sub-pixel array, a plurality of first wires extending along the row direction or the column direction, and a plurality of second wires which are parallel with the first wires. The plurality of sub-pixels includes transmissive sub-pixels and reflective sub-pixels. Each row and column in the sub-pixel array has both transmissive sub-pixels and reflective sub-pixels. The transmissive sub-pixels are connected to and driven by the first wires, and the reflective sub-pixels are connected to and driven by the second wires.

Abstract: A display device is provided. In the display device, sub-pixels are coupled to scan lines and data lines. On the same scan line, the sub-pixels with a predetermined number are belonged into a pixel group. For two pixel groups coupled to the same data lines and respectively coupled to two adjacent scan lines, two sub-pixels, which are respectively belonged into the two pixel groups and successively receive the corresponding data signals in time, receive the same one of the various color information. For each pixel group, in each display period, the enable states of the clock signals have a plurality of combinations having a specific number, the specific number is 2×CK2, where C represents two clock signals are selected from the clock signal having the predetermined number, and K is a positive integer.

Abstract: A transflective type liquid crystal panel includes a plurality of sub-pixels arranged in rows and columns to form a sub-pixel array, a plurality of first wires extending along the row direction or the column direction, and a plurality of second wires which are parallel with the first wires. The plurality of sub-pixels includes transmissive sub-pixels and reflective sub-pixels. Each row and column in the sub-pixel array has both transmissive sub-pixels and reflective sub-pixels. The transmissive sub-pixels are connected to and driven by the first wires, and the reflective sub-pixels are connected to and driven by the second wires.

Abstract: A display apparatus includes a multiplexer circuit, a driving unit, a first control line and a second control line. The multiplexer circuit includes a plurality of switch units. The first control line is electrically connected with the switch units and the driving unit. The second control line is electrically connected with the switch units and the driving unit. A maximum time constant from the driving unit to the switch units is less than R*C/4, wherein R represents the equivalent resistance of the portion of the first control line between the two switch units which are the farthest from each other, and C represents the equivalent capacitance of the portion of the first control line between the two switch units which are the farthest from each other.

Abstract: A shift register apparatus including a first shift register cell is disclosed. The first shift register cell includes a first logic unit, a first control unit and a first output unit. The first logic unit generates a first control signal and a second control signal according to a start signal and a first setting signal. During a first period, the first control unit employs the first and second control signals to make a first clock signal update the first setting signal and the first output unit employs the first and second control signals to make a second clock signal update the first shifted signal. During a second period, the first output unit controls the first shifted signal according to the first and second control signals such that the first shifted signal does not follow the second clock signal.

Abstract: A shift register apparatus including a first shift register cell is disclosed. The first shift register cell includes a first logic unit, a first control unit and a first output unit. The first logic unit generates a first control signal and a second control signal according to a start signal and a first setting signal. During a first period, the first control unit employs the first and second control signals to make a first clock signal update the first setting signal and the first output unit employs the first and second control signals to make a second clock signal update the first shifted signal. During a second period, the first output unit controls the first shifted signal according to the first and second control signals such that the first shifted signal does not follow the second clock signal.

Abstract: The digital-to-analog converter in accordance with the present invention comprises an R-2R transistor-only ladder converter and a digital controller. The controller connects to the R-2R transistor-only ladder converter and comprises at least one regulating transistor and at least one shifting transistor. The at least one regulating transistor has an aspect ratio of kR(W/L). The at least one shifting transistor has an aspect ratio of kS(W/L). Setting the aspect ratios kR(W/L) and kS(W/L) of the shifting and regulating transistors adjusts a linear output current waveform to a non-linear waveform. The method to output a non-linear current comprises acts of determining an optimum non-linear output current, dividing a linear output current into multiple sections, determining slopes of the waveform of the output current, adding a controller corresponding to an R-2R transistor-only ladder converter, setting aspect ratios kR(W/L) of regulating transistors and setting an aspect ratios kS(W/L) of shifting transistors.

Abstract: The digital-to-analog converter in accordance with the present invention comprises an R-2R transistor-only ladder converter and a digital controller. The controller connects to the R-2R transistor-only ladder converter and comprises at least one regulating transistor and at least one shifting transistor. The at least one regulating transistor has an aspect ratio of kR(W/L). The at least one shifting transistor has an aspect ratio of kS(W/L). Setting the aspect ratios kR(W/L) and kS(W/L) of the shifting and regulating transistors adjusts a linear output current waveform to a non-linear waveform. The method to output a non-linear current comprises acts of determining an optimum non-linear output current, dividing a linear output current into multiple sections, determining slopes of the waveform of the output current, adding a controller corresponding to an R-2R transistor-only ladder converter, setting aspect ratios kR(W/L) of regulating transistors and setting an aspect ratios kS(W/L) of shifting transistors.