Patents by Inventor Cheng Hsieh

Cheng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250007456
    Abstract: A frequency generating device and an operation method thereof are provided. The frequency generating device includes an oscillator circuit and a processor circuit. The oscillator circuit generates a clock signal and adjust a clock frequency of the clock signal according to a control voltage generated by the processor circuit. The processor circuit calculates a current frequency aging rate value based on a current clock frequency. The processor circuit calculates a control voltage regulation rate value based on the current frequency aging rate value and a control voltage slope, and compensates the control voltage based on the control voltage regulation rate value in the holdover state. Alternatively, the processor circuit calculates a frequency regulation value based on the current frequency aging rate value and an oscillator resolution of the synchronizer, and provides the frequency regulation value to the synchronizer in the holdover state to compensate an output frequency of the synchronizer.
    Type: Application
    Filed: September 12, 2024
    Publication date: January 2, 2025
    Applicant: TXC Corporation
    Inventors: Wan-Lin Hsieh, Wen-Cheng Wang, Sheng-Hsiang Kao
  • Patent number: 12183721
    Abstract: An electronic device includes a substrate, a spacer, a first element and a second element. The spacer is disposed on the substrate and has a first portion, a second portion, a first opening, a second opening and a third opening arranged in a first direction. In a cross-section view, the second opening is located between the first opening and the third opening, the first portion is located between the first opening and the second opening, and the second portion is located between the second opening and the third opening. A width of the first portion is less than a width of the second portion in the first direction, and an area of the second opening is different from an area of the first opening. The first element is overlapped with the first opening. The second element is overlapped with the third opening.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: December 31, 2024
    Assignee: Innolux Corporation
    Inventors: Jian-Jung Shih, Tsau-Hua Hsieh, Fang-Ying Lin, Kai Cheng
  • Patent number: 12179626
    Abstract: A structure for holding a battery on an automated guided vehicle (AGV) so as to allow easy and convenient battery replacement includes two fixed supports and a bracket. The bracket is connected between the two supports and each support defines a vertical groove and two horizontal grooves. Two sliders at the ends of the bracket are insertable into either horizontal groove. The two sliders can move down along the vertical groove together until the bracket makes contact with the battery and holds it in place. The two sliders can move up along the vertical groove and sideways into the horizontal grooves, thereby unlatching and releasing the battery for rapid replacement. An AGV using the structure is also disclosed.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: December 31, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hun-Yi Chou, Chih-Cheng Lee, Yu-Sheng Chang, Yu-Cheng Zhang, Hsiu-Fu Li, Chang-Ju Hsieh, Tsung-Hsin Wu, Chiung-Hsiang Wu, Chen Chao, Chen-Ting Kao, Chi-Cheng Wen, Sheng-Li Yen
  • Patent number: 12176299
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Chun-Yen Lan, Tzu-Ting Chou, Tzu-Shiun Sheu, Chih-Wei Lin, Shih-Peng Tai, Wei-Cheng Wu, Ching-Hua Hsieh
  • Patent number: 12176297
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tzu-Cheng Lin, Chun-Jen Chen
  • Publication number: 20240413220
    Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.
    Type: Application
    Filed: September 27, 2023
    Publication date: December 12, 2024
    Inventors: Wan Chen Hsieh, Zhen-Cheng Wu, Tai-Jung Kuo
  • Publication number: 20240413199
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.
    Type: Application
    Filed: August 22, 2024
    Publication date: December 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Kai-Lin Lee
  • Publication number: 20240413200
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.
    Type: Application
    Filed: August 22, 2024
    Publication date: December 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Kai-Lin Lee
  • Patent number: 12165936
    Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui Fu Hsieh, Chia-Chi Yu, Chih-Teng Liao, Yi-Jen Chen, Chia-Cheng Tai
  • Patent number: 12160013
    Abstract: A robot includes a limit device and an energy storehouse, the limiting device may lock or loosen a battery opened in the energy storehouse, the limiting device includes a first connecting member, a transmission rod, and a second connecting member. The first connecting member includes a first main body portion and two first connecting elements arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod includes a first end and a second end arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member includes two indexing buckles arranged at intervals, each of the indexing buckles includes a first limiting groove and a second limiting groove.
    Type: Grant
    Filed: February 21, 2024
    Date of Patent: December 3, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
  • Publication number: 20240395638
    Abstract: A semiconductor structure comprises: a semiconductor substrate; one or more first implant layers disposed in the semiconductor substrate and forming a circuit portion and a first test portion, the circuit portion forming an at least partially formed semiconductor circuit; and one or more second implant layers disposed in the semiconductor substrate and further forming the circuit portion and a second test portion, wherein the first and second test portions are spaced apart. A first implantation profile of the one or more first implant layers of the first test portion is obtained during a testing procedure, and the first implantation profile is a representation of a second implantation profile of the one or more first implant layers of the circuit portion.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Feng-Chien Hsieh, Kuo-Cheng Lee, Yun-Wei Cheng, Chun-Hao Lin, Ting-Hao Chang
  • Patent number: 12154933
    Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chien Hsieh, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
  • Publication number: 20240387256
    Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yao-Min LIU, Ming-Yuan GAO, Ming-Chou CHIANG, Shu-Cheng CHIN, Huei-Wen HSIEH, Kai-Shiang KUO, Yen-Chun LIN, Cheng-Hui WENG, Chun-Chieh LIN, Hung-Wen SU
  • Publication number: 20240387595
    Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chien HSIEH, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
  • Publication number: 20240387543
    Abstract: The proposed L-shaped field effect transistor comprises a horizontal FET and a vertical FET, wherein one end of the former is in contact with one end of the latter. Thus, the gates (or gate channels) of the two FETs can be separated by a distance so as to reduce mutual interference and simplify fabrication. When the two transistors are made of different materials, the contact area therebetween is small and the gates (or gate channels) of the two FETs are separated by a distance. Thus, the negative effect of interface defects close to the contact area can be reduced. To be compared to planar complementary FET (even FinFET and GAAFET), the proposed L-shaped FET can occupy a similar wafer area and have a similar overall thickness after subsequent metallization.
    Type: Application
    Filed: May 7, 2024
    Publication date: November 21, 2024
    Inventors: YEONG-HER WANG, CHIN-CHENG HSIEH, CHIUNG-YI YANG, DARSEN DUANE LU, YAO-JEN LEE
  • Patent number: 12144493
    Abstract: A collection and test device for a rapid test is provided. The device comprises a test fluid accommodation part having a test fluid accommodation space, a test paper accommodation part having a test paper accommodation space, and a collection probe having a channel for the test fluid to flow out from the collection probe. The two ends of the test paper accommodation part are respectively connected to the test fluid accommodation part and the collection probe, and the test paper accommodation space communicates with the channel of the collection probe. The test fluid accommodation space and the test paper accommodation space are separated from each other by a temporary barrier. The temporary barrier can be manually removed or broken to make the test fluid accommodation space communicate with the test paper accommodation space. The device of the present invention can provide the test results conveniently and rapidly.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: November 19, 2024
    Assignee: NATIONAL DEFENSE MEDICAL CENTER
    Inventors: Jia-En Chen, Juin-Hong Cherng, Yuan-Hao Chen, Cheng-Che Liu, Cheng-Cheung Chen, Yu-Min Tsai, Chin-Hsieh Yi
  • Publication number: 20240379815
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Bor Chiuan Hsieh, Tsai-Jung Ho, Po-Cheng Shih, Tze-Liang Lee
  • Publication number: 20240379470
    Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Jui Fu Hsieh, Chia-Chi Yu, Chih-Teng Liao, Yi-Jen Chen, Chia-Cheng Tai
  • Patent number: 12134159
    Abstract: A workpiece orientation mechanism includes: a driving device including a transmission motor and a controller which are connected with each other via signal, the transmission motor defining an axial direction; a rotating seat, combined with the transmission motor, and capable of being driven to rotate by the transmission motor; an orientation head disposed on the rotating seat to rotate synchronously with the rotating seat, wherein the orientation head is capable of moving along the axial direction relative to the rotating seat, one end of the orientation head includes a mounting head, and a blocking member is disposed on the orientation head; reset means, arranged between the rotating seat and the orientation head, and positioning the orientation head at a predetermined position; and a sensor facing the blocking member, wherein the sensor is signally connected with the controller.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: November 5, 2024
    Assignee: Hiwin Technologies Corp.
    Inventors: Chen-Yu Hsieh, Jhao-Jhong Su, Bo-Chen Lin, Kuo-Cheng Huang
  • Publication number: 20240363461
    Abstract: A device including a substrate, a front-end module circuit situated over the substrate and configured to provide radio frequency communications, and a wafer-level chip-scale package circuit situated over the front-end module circuit and connected to the front-end module circuit and configured to provide passive components for radio frequency communications.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Hsieh-Hung Hsieh, Chen Cheng Chou, Hwa-Yu Yang, Ming-Da Cheng, Ru-Shang Hsiao, Tzu-Jin Yeh, Ching-Hui Chen, Shenggao Li