Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, and a conductive filler. The polymer matrix has a fluoropolymer. The total volume of the PTC material layer is calculated as 100%, and the fluoropolymer accounts for 47-62% by volume of the PTC material layer. The fluoropolymer has a melt viscosity higher than 3000 Pa·s.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a first conductive filler. The polymer matrix includes a polyolefin-based polymer and a fluoropolymer. The fluoropolymer has a melt flow index higher than 1.9 g/10 min, and the polyolefin-based polymer and the fluoropolymer together form an interpenetrating polymer network (IPN). The first conductive filler has a metal-ceramic compound dispersed in the polymer matrix.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.

Abstract: A vehicle door epidemic prevention device applied to a public transportation vehicle is disposed on the public transportation vehicle, especially a bus. The public transportation vehicle has at least one door. The door has a doorway for passengers to enter and exit. The doorway is provided with at least one door panel. The door panel is provided with at least one disinfection unit. The disinfection unit faces the doorway when the door panel is in an open position. The disinfection unit is connected with a control unit for activating the disinfection unit to disinfect the passengers passing through the doorway when the door panel is in the open position, so as to achieve the purpose of epidemic prevention.

Abstract: A testing device includes a switch, a sensing circuit, and a control circuit. The switch is coupled to a power supply circuit, and the power supply circuit is configured to output a supply voltage to a device under-test via the switch. The sensing circuit is coupled to the device under-test, and the sensing circuit is configured to receive an input voltage from the device under-test and to output a sensing signal according to the input voltage. The control circuit is coupled to the sensing circuit, the power supply circuit, and the switch. The control circuit is configured to control the power supply circuit to stop outputting the supply voltage at a first time and to turn off the switch at a second time according to the sensing signal.

Abstract: A testing device includes a switch, a sensing circuit, and a control circuit. The switch is coupled to a power supply circuit, and the power supply circuit is configured to output a supply voltage to a device under-test via the switch. The sensing circuit is coupled to the device under-test, and the sensing circuit is configured to receive an input voltage from the device under-test and to output a sensing signal according to the input voltage. The control circuit is coupled to the sensing circuit, the power supply circuit, and the switch. The control circuit is configured to control the power supply circuit to stop outputting the supply voltage at a first time and to turn off the switch at a second time according to the sensing signal.

Abstract: A pulse generating apparatus capable of calibration and calibrating method are disclosed. The pulse generating apparatus includes a pulse generator and a delay detector. The pulse generator is configured to repeatedly generate a testing pulse. The delay detector is electrically connected with the pulse generator. When the pulse generator generates the testing pulse, the delay detector detects a feature value of the testing pulse at a plurality detecting time points, and calculates a calibration value according to the detected feature values. The delay detector outputs the calibration value to the pulse generator and the pulse generator adjusts the testing pulse according to the calibration value.

Abstract: A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to the first timing delay module. The second timing delay module is electrically connected to the multiplexer. The first timing delay module generates a plurality of delayed clock signals based on a reference clock signal. The multiplexer outputs a first delayed clock signal and a second delayed clock signal, among the plurality of delayed clock signals, based on a clock generating signal. The second timing delay module generates an output clock signal based on the clock generating signal, the first delayed clock signal and the second delayed clock signal.

Abstract: Aspects of the disclosure provide a method for call management. The method includes receiving a signal from one of a first transceiver and a second transceiver in an electronic device. The signal indicates an incoming call managed by a first service provider that the electronic device subscribes service from. The method further includes determining whether the other of the first transceiver and the second transceiver is operative in an active call managed by a second service provider that the electronic device subscribes service from, and rejecting the incoming call when the other transceiver is operative in the active call managed by the second service provider.

Abstract: A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to the first timing delay module. The second timing delay module is electrically connected to the multiplexer. The first timing delay module generates a plurality of delayed clock signals based on a reference clock signal. The multiplexer outputs a first delayed clock signal and a second delayed clock signal, among the plurality of delayed clock signals, based on a clock generating signal. The second timing delay module generates an output clock signal based on the clock generating signal, the first delayed clock signal and the second delayed clock signal.

Abstract: Power is provided to a scanning device. Power supplied by an attached bus is used to power the scanning device when power requirements for the scanning device can be met by the power supplied by the attached bus. Power is drawn from a rechargeable battery to supply power to the scanning device when power requirements for the scanning device cannot be met by the power from the attached bus. When the scanning device is in a stand-by mode, the power from the attached bus is used to recharge the rechargeable battery.

Abstract: The invention provides a method for identifying a disk type of an optical disk in an optical disk drive. First, a pickup head of the optical disk drive is moved towards the optical disk. A reflected signal is then observed as said pickup head of the optical drive is moving on the optical disk. A motion behavior is then detected from said reflected signal. A first period between motion initiation of the pickup head and a first peak occurrence of the power of the reflected signal is then determined, the first peak occurrence take places while the pickup head detects said motion behavior of said reflected signal is in accordance with a motion reflected by an polycarbonate layer of the optical disk.

Abstract: Power is provided to a scanning device. Power supplied by an attached bus is used to power the scanning device when power requirements for the scanning device can be met by the power supplied by the attached bus. Power is drawn from a rechargeable battery to supply power to the scanning device when power requirements for the scanning device cannot be met by the power from the attached bus. When the scanning device is in a stand-by mode, the power from the attached bus is used to recharge the rechargeable battery.

Abstract: An electric fan includes a fan unit, and a processor unit coupled to the fan unit and operable so as to control the fan unit to rotate at a selected one of preset speed settings. The processor unit is operable in a breeze-simulating mode, wherein the processor unit controls the fan unit to operate in accordance with a programmed sequence of the preset speed settings and corresponding time durations, thereby enabling the fan unit to generate a simulated breeze output.

Abstract: An electric fan includes a fan unit, a temperature detector for generating a temperature output that varies in accordance with the ambient temperature, and a processor unit operable so as to control the fan unit to rotate at a selected one of preset speed settings, and further operable in an intelligent mode, wherein the processor unit determines a current selected one of the preset speed settings of the fan unit and receives the temperature output of the temperature detector so as to obtain a reference ambient temperature, and wherein the processor unit controls the fan unit to operate at a higher preset speed setting upon detection of a predetermined increase in the current ambient temperature, and at a lower preset speed setting upon detection of a predetermined decrease in the current ambient temperature.