Patents by Inventor Cheng-hsien Chiu

Cheng-hsien Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220418095
    Abstract: ESD suppressor and manufacturing method thereof. The ESD suppressor include at least two printed circuit boards, one insulating frame, two terminal electrodes and two or more interior electrodes. The insulating frame is positioned between the two printed circuit boards, so as to form a main structure with a cavity. For each printed circuit board, at least one interior electrode is positioned on the surface facing the cavity and separated from other interior electrode(s). Two terminal electrodes are positioned on two different surfaces of the main structure and electrically connected to different interior electrodes respectively. Optionally, the insulating frame is a hallowed out printed circuit board or a frame formed by printing insulating material.
    Type: Application
    Filed: August 9, 2021
    Publication date: December 29, 2022
    Inventors: CHING HOHN LIEN, HUNG TSUNG HSU, CHIH HSIEN HSU, CHENG HSIEN CHIU, HSING-TSAI HUANG
  • Publication number: 20200411470
    Abstract: A novel packaging method for attached (SMD-type) single small-size and array type chip semiconductor components is disclosed. The configuration of circuit board(s) with double-side interconnections includes reserving two or more connection endpoints on the inner and outer layers of a double-sided circuit board, and interconnecting the circuits on the inner and outer layers by hole drilling and electroplating, such that the two or more connection endpoints on the inner layer are used as inner electrodes for connecting with a semiconductor die, whereas the two or more connection endpoints on the outer layer are used as outer electrodes for SMT soldering.
    Type: Application
    Filed: August 9, 2019
    Publication date: December 31, 2020
    Inventors: Ching-Hohn Len, Hsing-Hsiang Huang, Hsing-Tsai Huang, Cheng Hsien Chiu
  • Patent number: 7416920
    Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: August 26, 2008
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
  • Patent number: 7400037
    Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 15, 2008
    Assignee: Advanced Chip Engineering Tachnology Inc.
    Inventors: Wen-Kun Yang, Chin-Chen Yang, Cheng-hsien Chiu, Wen-Bin Sun, Kuang-Chi Chao, His-Ying Yuan, Chun-Hui Yu
  • Publication number: 20070082428
    Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 12, 2007
    Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
  • Patent number: 7176567
    Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: February 13, 2007
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
  • Publication number: 20070007648
    Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.
    Type: Application
    Filed: July 6, 2005
    Publication date: January 11, 2007
    Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
  • Publication number: 20060145364
    Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Wen-Kun Yang, Chin-Chen Yang, Cheng-hsien Chiu, Wen-Bin Sun, Kuang-Chi Chao, His-Ying Yuan, Chun-Hui Yu