Abstract: A semiconductor device includes a semiconductor substrate, and a redistribution layer (RDL) over the semiconductor substrate and configured to receive a bump. The semiconductor device further includes a polymeric material over the RDL, and the polymeric material includes an opening to expose a portion of the RDL. In the semiconductor device, a barrier is covering a joint between the polymeric material and the RDL.

Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.

Abstract: A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.

Abstract: Package structures and methods of forming the same are disclosed. A package structure includes a die, a dielectric layer, an encapsulant and a plurality of supports. The die includes, over a first side thereof, a plurality of connectors. The dielectric layer is formed over the first side of the die aside the connectors. The encapsulant is aside the die. The supports penetrate through the dielectric layer. The grinding rate of the supports is substantially the same as that of the encapsulant but different from that of the dielectric layer.

Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: An assembled wearable electronic device includes a first body, a second body and an engaging assembly. The first body has a primary system for providing the independent operation of the first body and producing a related first data. The second body has a secondary system and a fixing assembly. The secondary system is for providing the independent operation of the second body and producing a related second data. The engaging assembly is disposed at one of the first and second bodies. When the engaging assembly is located at a first position, the first and second bodies contact each other to be combined through the engaging assembly. When the engaging assembly moves to a second position, the first and second bodies are configured to be separated from each other. When the first and second bodies are connected to each other, the second data is read by the primary system.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: A catalytic article for destruction of a volatile organic compound includes a porous carrier body, a plurality of catalyst units formed on the carrier body and adapted for destruction of the volatile organic compound, and a plurality of trapping molecules bound to the carrier body. Each of the catalyst units is composed of one of a noble metal, a transition metal oxide, and the combination thereof. Each of the trapping molecules includes at least one functional group that is adapted for attracting or binding the volatile organic compound. A method for preparing the catalytic article is also disclosed.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A catalytic article for decomposition of a volatile organic compound includes a porous support body, a plurality of active centers formed on the support body and adapted for catalytic decomposition of the volatile organic compound, and a plurality of capture centers bound to the support body. Each of the active centers is composed of one of a noble metal, a transition metal oxide, and the combination thereof. Each of the capture centers includes at least one functional group that is adapted for attracting or binding the volatile organic compound. A method for preparing the catalytic article is also disclosed.