Abstract: A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.

Abstract: Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.

Abstract: Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.

Abstract: Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.

Abstract: An electrical assembly includes (a) a first inductor including a first winding wound around a first winding axis, (b) a second inductor separated from the first inductor in a first direction, and (c) a coupler at least partially disposed between the first inductor and the second inductor in the first direction, the coupler forming at least part of an electrical circuit enabling electric current to flow through the coupler, and the coupler being asymmetric with respect to a dividing axis of the first inductor extending in a second direction that is orthogonal to the first direction.

Abstract: A near field communication reader includes a receiver, a transmitter, a matching network, a reader antenna coupled to the matching network; a microcontroller coupled to the receiver and the transmitter, a microcontroller; and a non-transitory computer readable media coupled to the microcontroller and including code segments and data executable on the microcontroller to control a RF driver of the transmitter based upon loading level as determined, for example, by a field detector output and RF driver settings.

Abstract: A near field communication reader includes a receiver, a transmitter, a matching network, a reader antenna coupled to the matching network; a microcontroller coupled to the receiver and the transmitter, a microcontroller; and a non-transitory computer readable media coupled to the microcontroller and including code segments and data executable on the microcontroller to control a RF driver of the transmitter based upon loading level as determined, for example, by a field detector output and RF driver settings.

Abstract: An adaptive dual mode card emulation system (in Card Emulation Mode or PICC design) within an NFC device is disclosed to solve the strong field power delivering issue and also achieve longer communication range. The NFC device may be a NFC tag or an electronic device (such as a smartphone) operated in a card emulation mode. The NFC device comprises an antenna used for wireless communication. The adaptive dual mode card emulation system comprises a passive load modulation (PLM) module, an active load modulation (ALM) module and an automatic power control (APC) module. The APC module couples to both the ALM and PLM modules and selectably enables the ALM or PLM module depending on the strength of received carrier signal sent from an NFC reader.

Abstract: An antenna includes a plurality of upper electrodes in a first metal layer, a plurality of lower electrodes in a second metal layer, a plurality of side electrodes connecting the upper electrodes with the lower electrodes, and a ground structure. The upper electrodes, the lower electrodes and the side electrodes form one continuous electrode. The continuous electrode extends in a first direction away from a reference plane over a substrate. The upper electrodes extend in a second direction different from the first direction. The upper electrodes, the lower electrodes, and the side electrodes are embedded within a waveguide structure that includes a dielectric material. The substrate has a length extending in the first direction greater than a length the continuous electrode extends in the first direction. The waveguide structure includes a portion of the substrate in a region beyond the length of the continuous electrode in the first direction.

Abstract: An adaptive dual mode card emulation system (in Card Emulation Mode or PICC design) within an NFC device is disclosed to solve the strong field power delivering issue and also achieve longer communication range. The NFC device may be a NFC tag or an electronic device (such as a smartphone) operated in a card emulation mode. The NFC device comprises an antenna used for wireless communication. The adaptive dual mode card emulation system comprises a passive load modulation (PLM) module, an active load modulation (ALM) module and an automatic power control (APC) module. The APC module couples to both the ALM and PLM modules and selectably enables the ALM or PLM module depending on the strength of received carrier signal sent from an NFC reader.

Abstract: An antenna includes a plurality of upper electrodes in a first metal layer, a plurality of lower electrodes in a second metal layer, a plurality of side electrodes connecting the upper electrodes with the lower electrodes, and a ground structure. The upper electrodes, the lower electrodes and the side electrodes form one continuous electrode. The continuous electrode extends in a first direction away from a reference plane over a substrate. The upper electrodes extend in a second direction different from the first direction. The upper electrodes, the lower electrodes, and the side electrodes are embedded within a waveguide structure that includes a dielectric material. The substrate has a length extending in the first direction greater than a length the continuous electrode extends in the first direction. The waveguide structure includes a portion of the substrate in a region beyond the length of the continuous electrode in the first direction.

Abstract: A rectangular helix antenna in an integrated circuit includes upper electrodes disposed in a first metal layer, lower electrodes disposed in a second metal layer, and side electrodes connecting the upper electrodes with the lower electrodes, respectively. The upper electrodes are disposed at an angle with respect to the lower electrodes. The upper electrodes, the lower electrodes, and the side electrodes form one continuous electrode spiraling around an inner shape of a rectangular bar. A micro-electromechanical system (MEMS) helix antenna has a similar structure to the rectangular helix antenna, but can have an inner shape of a bar.

Abstract: A system and method for persistent ID flag for RFID applications includes a method for operating an RFID tag. The method includes measuring a voltage potential of a supply voltage for the RFID tag, and turning on a pass gate that couples a memory cell to a data line used for reading or writing data, if the voltage potential is greater than a first threshold. An accumulated charge on the memory cell is also measured, and both the voltage potential and the accumulated charge are used to generate a control signal to set a state of the pass gate. The pass gate is turned off if the control signal is a true value.

Abstract: A rectangular helix antenna in an integrated circuit includes upper electrodes disposed in a first metal layer, lower electrodes disposed in a second metal layer, and side electrodes connecting the upper electrodes with the lower electrodes, respectively. The upper electrodes are disposed at an angle with respect to the lower electrodes. The upper electrodes, the lower electrodes, and the side electrodes form one continuous electrode spiraling around an inner shape of a rectangular bar. A micro-electromechanical system (MEMS) helix antenna has a similar structure to the rectangular helix antenna, but can have an inner shape of a bar.

Abstract: A system and method for persistent ID flag for RFID applications includes a method for operating an RFID tag. The method includes measuring a voltage potential of a supply voltage for the RFID tag, and turning on a pass gate that couples a memory cell to a data line used for reading or writing data, if the voltage potential is greater than a first threshold. An accumulated charge on the memory cell is also measured, and both the voltage potential and the accumulated charge are used to generate a control signal to set a state of the pass gate. The pass gate is turned off if the control signal is a true value.

Abstract: This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.

Abstract: A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance.

Abstract: A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance.

Abstract: This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.

Abstract: This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source.