Patents by Inventor Cheng-Hsin Ma

Cheng-Hsin Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8399158
    Abstract: Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventors: Chang Ju Choi, Cheng-Hsin Ma, Sven Henrichs, Robert H. Olshausen, Yulia Korobko
  • Publication number: 20120164563
    Abstract: Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventors: Chang Ju Choi, Cheng-Hsin Ma, Sven Henrichs, Robert H. Olshausen, Yulia Korobko
  • Publication number: 20110159411
    Abstract: A phase shift photomask blank has a quartz substrate, a lower chrome layer, a light-absorbing MoSi layer, and an upper chrome layer. This mask can be patterned in various ways to form a patterned photomask with both phase shift and binary areas.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Bennett Olson, Max Lau, Cheng-hsin Ma, Jian Ma, Andrew T. Jamieson
  • Publication number: 20090001057
    Abstract: In one embodiment, a system to measure changes and a dual damascene trench depth, comprises a power source, and impedance matching network coupled to the power source and to an electrode, a radio frequency sensor coupled to the impedance matching network, and a controller to establish a baseline correlation between a plasma impedance and the dual damascene trench depth, and use the baseline correlation to measure changes in the dual damascene trench depth.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Cheng-Hsin Ma, Jeff J. Xu