Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract: A semiconductor circuit comprises a first and a second logic circuit, a first and a second decoupling capacitor. The first decoupling capacitor is arranged in a first area around the first logic circuit and the second decoupling capacitor is arranged in a second area around the second logic circuit. Wherein, the first area is larger than the second area, a gate oxide thickness of the first decoupling capacitor is larger than a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. Further, the first and second decoupling capacitors are designed without trench.

Abstract: The present disclosure presents a signal regulation device for an oxygen sensor which features a voltage regulation module connected between an automobile system and an oxygen sensor in series through an input module and an output module, changing initial voltage generated by the oxygen sensor, transmitting regulated voltage to the automobile system via the output module, and interfering with a catalytic converter for processed oxygen content to be detected by the oxygen sensor.

Abstract: A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor.

Abstract: A barbecue gridiron includes an upper board part, and a lower board part; the upper and the lower board parts have many meshes thereon; the upper and the lower board parts are secured together to constitute a mesh-like barbecue gridiron member; the meshes of the upper board part each face a corresponding mesh of the lower board part; the upper and the lower board parts are connected at outer peripheries as well as those portions that are around the meshes such that a hermetic holding space exists between the upper and the lower board parts; water is contained in the hermetic holding space; when food materials are being roasted on the barbecue gridiron over a fire, water will circulate in the hermetic holding space to help prevent temperature of the mesh-like barbecue gridiron member from getting too high, thus preventing the food materials from being scorched to be unpalatable.

Abstract: A barbecue gridiron includes a hollow pipe; the hollow pipe winds so as to become a mesh-like barbecue gridiron member including many pipe sections, which are in communication with and substantially parallel to each other; connecting pipes are connected to two ends of the winding hollow pipe respectively, and a pump is connected to the connecting pipes to pump water into the winding hollow pipe, i.e. the mesh-like barbecue gridiron member; when food materials are being roasted on the barbecue gridiron over a fire, water will be circulated in the winding hollow pipe so as to help to prevent temperature of the winding hollow pipe from getting too high; consequently, the food materials are prevented from being scorched to be unpalatable before they become cooked.

Abstract: An integrated circuit and method for simulating and trimming the same are provided. The integrated circuit includes a multiplexer, a trimming circuit, a major circuit, and a simulating device. The simulating device simulates the operation of the trimming circuit and sends a simulating signal to temporarily change the electric characteristics. Hence, the electric characteristics of the integrated circuit after trimming can be predicted so that the difference between the predicted and real electric characteristics can be reduced and the yield rate can be effectively improved.

Abstract: In a preferred embodiment of the present invention, a bidirectional buffer connects a first device, such as a CMOS chip having a first voltage, such as VDD, to a second device having a second voltage, such as VCC, through a terminal pad. The buffer includes a first driver for driving a terminal pad up to the first voltage, wherein the first driver preferably includes a pair of in series PMOS transistors formed in an n floating well. The buffer further includes a second driver for driving the terminal pad down to a voltage VSS. Such a structure provides a simple circuit that requires only a single terminal pad, a single power supply, and is substantially free of dc leakage currents.