Patents by Inventor Cheng-Hsing Hsu

Cheng-Hsing Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110231330
    Abstract: A job matching method that matches applicants with employers is revealed. The job matching method includes steps of providing a plurality pieces of capability information of a job seeker, creating a capability map by quantifying the pieces of capability information, and matching the capability map with a plurality of recruitment requirements. Thus the job applicant's capabilities are shown by the capability map clearly and the employers find qualified candidates more quickly. The length of the interview is reduced and the recruitment period is minimized. Therefore, the recruitment is more efficient.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 22, 2011
    Applicant: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: CHENG-HSING HSU, YUH-SHOW TSAI, CHING-JUNG LIAO
  • Patent number: 7539065
    Abstract: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 26, 2009
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Hsing Hsu, Hao-Ming Lien
  • Publication number: 20080056009
    Abstract: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 6, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsing Hsu, Hao-Ming Lien
  • Patent number: 7307882
    Abstract: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: December 11, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Cheng-Hsing Hsu, Hao-Ming Lien
  • Patent number: 7218554
    Abstract: A method of using a non-volatile memory that utilizes a charge-trapping layer for data storage is described. A refresh step is performed, after the non-volatile memory is subject to multiple write/erase cycles causing hard-to-erase electrons in the charge-trapping layer, to eliminate the hard-to-erase electrons. After the refresh step, the non-volatile memory is used again.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: May 15, 2007
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Hsing Hsu, Chao-I Wu, Hao-Ming Lien, Ming-Hsiang Hsueh
  • Publication number: 20070001210
    Abstract: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Cheng-Hsing Hsu, Hao-Ming Lien
  • Publication number: 20060279997
    Abstract: A method of using a non-volatile memory that utilizes a charge-trapping layer for data storage is described. A refresh step is performed, after the non-volatile memory is subject to multiple write/erase cycles causing hard-to-erase electrons in the charge-trapping layer, to eliminate the hard-to-erase electrons. After the refresh step, the non-volatile memory is used again.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 14, 2006
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHENG-HSING HSU, CHAO-I WU, HAO-MING LIEN, MING-HSIANG HSUEH