Patents by Inventor Cheng-Hsu Wu
Cheng-Hsu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145898Abstract: An electronic device including a metal casing and at least one antenna module is provided. The metal casing includes at least one window. The at least one antenna module is disposed in the at least one window. The at least one antenna module includes a first radiator and a second radiator. The first radiator includes a feeding end, a first ground end joined to the metal casing, a second ground end, a first portion extending from the feeding end to the first ground end, and a second portion extending from the feeding end to the second ground end. A first coupling gap is between the second radiator and the first portion. A second coupling gap is between at least part of the second radiator and the metal casing, and the second radiator includes a third ground end joined to the metal casing.Type: ApplicationFiled: September 8, 2023Publication date: May 2, 2024Applicant: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chih-Wei Liao, Hau Yuen Tan, Cheng-Hsiung Wu, Shih-Keng Huang
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Publication number: 20240138709Abstract: A care system monitoring method for sensing the movement state of a bedridden person is provided. The care system monitoring method includes the following stages. Initial-state information is sensed. A first warning signal is issued to remind the caregiver to perform a movement action on the bedridden person when the time that the bedridden person has been in the initial state exceeds the threshold period. First-state information (which is information that is collected when the bedridden person is in the first state) is sensed after completing the movement action. It is determined whether the bedridden person was moved correctly according to the initial-state information and the first-state information. The first-state information is reset as the initial-state information if it is determined that the bedridden person has been moved correctly. A second warning signal is issued if it is determined that the bedridden person has been moved incorrectly.Type: ApplicationFiled: September 7, 2023Publication date: May 2, 2024Inventors: Cheng-Hsu CHOU, Wei-Chih LIU, Fang-Iy WU
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Patent number: 11955707Abstract: An antenna module includes first to third radiators and a ground radiator. The first radiator includes first and second sections and excites at a first frequency band. An extension direction of the first section, including a feeding end, is not parallel to an extension direction of the second section. The second radiator includes third and fourth sections. The third section extends from an intersection of the first and second sections. The third section excites at a second frequency band. The third radiator is disposed beside the first radiator and away from the second radiator. The ground radiator is disposed on one side of the first, second, and third radiators, and includes a ground end. The fourth section of the second radiator is connected to the third section and the ground radiator. The third radiator is connected to the ground end.Type: GrantFiled: April 19, 2022Date of Patent: April 9, 2024Assignee: PEGATRON CORPORATIONInventors: Chao-Hsu Wu, Hau Yuen Tan, Chien-Yi Wu, Shih-Keng Huang, Cheng-Hsiung Wu, Ching-Hsiang Ko
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Patent number: 11937932Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: GrantFiled: July 8, 2022Date of Patent: March 26, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
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Publication number: 20240066313Abstract: An electronic device includes a light emitting layer, a light conversion layer and an adjustable structure. The light emitting layer has a plurality of light emitting units for emitting light. The light conversion layer converts the wavelength of the light emitted by at least one light emitting unit to provide converted light. The adjustable structure is controlled to adjust a light penetrating area to correspond to the affected part to be treated, wherein at least one of the light and the converted light passes through the light penetrating area to irradiate the affected part.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Inventors: Jih-Ping LIN, Chun-Kai LEE, Fang-Iy WU, Cheng-Hsu CHOU
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Patent number: 11258252Abstract: The present invention provides an on-chip surge protection circuit, including a low voltage rail, a negative transmitter differential output, a positive transmitter differential output, and a surge protection component. The surge protection component includes a first end, a second end, and a control end. The first end is connected to the transmitter differential output N. The second end is connected to the transmitter differential output P. The control end is connected to the low voltage rail.Type: GrantFiled: January 31, 2020Date of Patent: February 22, 2022Assignee: ECONET (HK) LIMITEDInventors: Cheng-Hsu Wu, Cheng-Chieh Hsu, Che-Yuan Jao, Hung-Wei Chen, Tsung-Hsien Hsieh
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Publication number: 20210159693Abstract: The present invention provides an on-chip surge protection circuit, including a low voltage rail, a negative transmitter differential output, a positive transmitter differential output, and a surge protection component. The surge protection component includes a first end, a second end, and a control end. The first end is connected to the transmitter differential output N. The second end is connected to the transmitter differential output P. The control end is connected to the low voltage rail.Type: ApplicationFiled: January 31, 2020Publication date: May 27, 2021Inventors: Cheng-Hsu WU, Cheng-Chieh HSU, Che-Yuan JAO, Hung-Wei CHEN, Tsung-Hsien HSIEH
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Patent number: 10969596Abstract: Systems and methods for filtering an optical beam are described. In one implementation, a system for filtering an input optical beam includes a first beamsplitter, a first spectral slicing module, a second spectral slicing module, and a second beamsplitter. The first beamsplitter is configured to split the input optical beam into a first optical beam and a second optical beam. The first spectral slicing module has a first passband and is configured to filter the first optical beam. The second spectral slicing module has a second passband and is configured to filter the second optical beam. The second beamsplitter is configured to combine the first optical beam and the second optical beam into an output optical beam. The first and second spectral slicing modules may each comprise a longpass filter and a shortpass filter aligned along its optical axis, and the longpass filter and/or the shortpass filter are rotatable relative to the optical axis.Type: GrantFiled: March 7, 2019Date of Patent: April 6, 2021Assignee: Verily Life Sciences LLCInventors: Supriyo Sinha, Cheng-Hsu Wu
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Publication number: 20190204609Abstract: Systems and methods for filtering an optical beam are described. In one implementation, a system for filtering an input optical beam includes a first beamsplitter, a first spectral slicing module, a second spectral slicing module, and a second beamsplitter. The first beamsplitter is configured to split the input optical beam into a first optical beam and a second optical beam. The first spectral slicing module has a first passband and is configured to filter the first optical beam. The second spectral slicing module has a second passband and is configured to filter the second optical beam. The second beamsplitter is configured to combine the first optical beam and the second optical beam into an output optical beam. The first and second spectral slicing modules may each comprise a longpass filter and a shortpass filter aligned along its optical axis, and the longpass filter and/or the shortpass filter are rotatable relative to the optical axis.Type: ApplicationFiled: March 7, 2019Publication date: July 4, 2019Inventors: Supriyo Sinha, Cheng-Hsu Wu
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Patent number: 10241337Abstract: Systems and methods for filtering an optical beam are described. In one implementation, a system for filtering an input optical beam includes a first beamsplitter, a first spectral slicing module, a second spectral slicing module, and a second beamsplitter. The first beamsplitter is configured to split the input optical beam into a first optical beam and a second optical beam. The first spectral slicing module has a first passband and is configured to filter the first optical beam. The second spectral slicing module has a second passband and is configured to filter the second optical beam. The second beamsplitter is configured to combine the first optical beam and the second optical beam into an output optical beam. The first and second spectral slicing modules may each comprise a longpass filter and a shortpass filter aligned along its optical axis, and the longpass filter and/or the shortpass filter are rotatable relative to the optical axis.Type: GrantFiled: April 6, 2017Date of Patent: March 26, 2019Assignee: Verily Life Sciences LLCInventors: Supriyo Sinha, Cheng-Hsu Wu
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Publication number: 20170343825Abstract: Systems and methods for filtering an optical beam are described. In one implementation, a system for filtering an input optical beam includes a first beamsplitter, a first spectral slicing module, a second spectral slicing module, and a second beamsplitter. The first beamsplitter is configured to split the input optical beam into a first optical beam and a second optical beam. The first spectral slicing module has a first passband and is configured to filter the first optical beam. The second spectral slicing module has a second passband and is configured to filter the second optical beam. The second beamsplitter is configured to combine the first optical beam and the second optical beam into an output optical beam. The first and second spectral slicing modules may each comprise a longpass filter and a shortpass filter aligned along its optical axis, and the longpass filter and/or the shortpass filter are rotatable relative to the optical axis.Type: ApplicationFiled: April 6, 2017Publication date: November 30, 2017Inventors: Supriyo Sinha, Cheng-Hsu Wu
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Patent number: 8009459Abstract: A memory cell includes a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.Type: GrantFiled: December 30, 2008Date of Patent: August 30, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsu Wu, David Yen, Tsai-Hsin Lai
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Publication number: 20100165704Abstract: A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Inventors: Cheng-Hsu Wu, David Yen, Tsai-Hsin Lai
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Patent number: 7566935Abstract: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell thaType: GrantFiled: March 1, 2007Date of Patent: July 28, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu Huei Lin, Jian Hsing Lee, Shao Chang Huang, Cheng Hsu Wu, Chuan Ying Lee
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Publication number: 20080211027Abstract: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell thaType: ApplicationFiled: March 1, 2007Publication date: September 4, 2008Inventors: Shu Huei Lin, Jian-Hsing Lee, Shao-Chang Huang, Cheng Hsu Wu, Chuan Ying Lee
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Patent number: 6428736Abstract: A method for forming a hollow bottom of an acrylic cup by forming a cup body by injecting a molding with a liquid transparent or semi-transparent acrylic material into a mold to form a mushroom shaped cavity. The cavity in the bottom of the cup body is filled with a gas, permitting the whole cup to appear to have a three dimensional (3D) visual effect. The cavity of the bottom of the cup can be filled with a non-colored or colored liquid to permit the whole cup to contain a deflected visual effect of a plurality of colored layers.Type: GrantFiled: August 11, 1999Date of Patent: August 6, 2002Inventor: Cheng-Hsu Wu
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Patent number: 6281061Abstract: The present invention discloses a method for fabricating isolation trenches applied in BiCMOS processes. The isolation trenches are formed initially by defining an oxide layer formed on a semiconductor substrate. Then an epitaxy layer is formed on the substrate and a polysilicon layer is formed on the oxide layer by selective epitaxial growth (SEG). After forming well regions and a collector region in the epitaxy layer, the polysilicon layer is etched and stopped at the oxide layer such that trenches are formed. Subsequently, an isolating material is filled into the trenches to form isolation trenches. It is noted that the oxide layer definition, the epitaxy layer and the polysilicon layer growth by SEG, and the polysilicon etching processes simplify the process of forming isolation trenches. In addition, the integration of the semiconductor is increased, and the isolating effect is good.Type: GrantFiled: May 22, 2000Date of Patent: August 28, 2001Assignee: United Microelectronics CorpInventors: Cheng-Hsu Wu, Chin Liang Chen