Patents by Inventor Cheng-Hsun Chung

Cheng-Hsun Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121698
    Abstract: A quartz oscillating plate comprises a substrate having a notch. Two sides of the notch respectively have a first side-electrode and a second side-electrode. The first side-electrode receives an external signal. The external signal is transmitted along the perimeter of the substrate. The notch of the substrate can increase the length of the transmission path of oscillation energy. The present invention can improve the Q value of the quartz oscillator using the quartz oscillating plate and optimize the performance of the products using the quartz oscillator.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 14, 2021
    Assignee: TXC Corporation
    Inventors: Yen-Chih Lee, Cheng-Hsun Chung, Chih-Hung Chiu, Min-Ho Wang
  • Publication number: 20190245511
    Abstract: A quartz oscillating plate comprises a substrate having a notch. Two sides of the notch respectively have a first side-electrode and a second side-electrode. The first side-electrode receives an external signal. The external signal is transmitted along the perimeter of the substrate. The notch of the substrate can increase the length of the transmission path of oscillation energy. The present invention can improve the Q value of the quartz oscillator using the quartz oscillating plate and optimize the performance of the products using the quartz oscillator.
    Type: Application
    Filed: October 25, 2018
    Publication date: August 8, 2019
    Inventors: YEN-CHIH LEE, CHENG-HSUN CHUNG, CHIH-HUNG CHIU, MIN-HO WANG
  • Publication number: 20180114858
    Abstract: A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.
    Type: Application
    Filed: June 23, 2017
    Publication date: April 26, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Cheng-Hsun Chung, Shih-Teng Huang, Tien-Shang Kuo
  • Patent number: 9954099
    Abstract: A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 24, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Hsun Chung, Shih-Teng Huang, Tien-Shang Kuo
  • Patent number: 9741826
    Abstract: A transistor structure including a substrate, a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on the substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 22, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Hsun Chung, Shih-Teng Huang, Tien-Shang Kuo