Patents by Inventor Cheng Hua LIN

Cheng Hua LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Publication number: 20240079483
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hung LIN, I-Hsieh WONG, Tzu-Hua CHIU, Cheng-Yi PENG, Chia-Pin LIN
  • Publication number: 20240072044
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 29, 2024
    Inventors: Cheng-Hua LIN, Yan-Liang JI
  • Patent number: 11705514
    Abstract: A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 18, 2023
    Assignee: MediaTek Inc.
    Inventors: Cheng Hua Lin, Yan-Liang Ji
  • Publication number: 20230187144
    Abstract: A capacitor structure includes a first comb-shaped electrode, a second comb-shaped electrode, a bottom electrode, an insulator layer, and a top electrode. The first comb-shaped electrode has a first pad and first fingers connecting to the first pad. The second comb-shaped electrode has a second pad and second fingers connecting to the first pad, wherein one of the second fingers is disposed between two adjacent first fingers. The bottom electrode includes a first portion, a second portion and a third portion which are spaced apart, wherein the first portion and the third portion are electrically coupled to the first comb-shaped electrode and the second comb-shaped electrode, respectively. The insulator layer is disposed over the bottom electrode. The top electrode is disposed over the insulator layer.
    Type: Application
    Filed: November 14, 2022
    Publication date: June 15, 2023
    Inventors: Je-Min WEN, Cheng-Hua LIN, Ching-Han JAN
  • Publication number: 20230038119
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a polysilicon resistive structure, dummy polysilicon resistive structures, and a polysilicon ring structure. The semiconductor substrate has an active region and a passive region adjacent to the active region. The polysilicon resistive structure is disposed on an isolation structure in the passive region. The dummy polysilicon resistive structures are disposed on the isolation structure, respectively disposed outside opposite sides of the polysilicon resistive structure. The polysilicon ring structure is disposed on the isolation structure, encircling the polysilicon resistive structure and the dummy polysilicon resistive structures.
    Type: Application
    Filed: July 8, 2022
    Publication date: February 9, 2023
    Inventors: Cheng-Hua LIN, Ching-Han JAN
  • Publication number: 20220384608
    Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The semiconductor device also includes a gate spacer structure having a first spacer portion and a second spacer portion on opposite sidewalls of the gate structure. The semiconductor device also includes a source region and a drain region formed in the semiconductor substrate. The source region and a drain region are separated from the gate structure. The source region is adjacent to the first spacer portion of the gate spacer structure, and the drain region is adjacent to the second spacer portion of the gate spacer structure. The bottom width of the second spacer portion is greater than the bottom width of the first spacer portion.
    Type: Application
    Filed: May 3, 2022
    Publication date: December 1, 2022
    Inventors: Cheng-Hua LIN, Yan-Liang JI, Ching-Han JAN
  • Publication number: 20220238712
    Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The gate structure has a first sidewall and a second sidewall. The second sidewall is opposite the first sidewall. The semiconductor device also includes a gate spacer structure having two asymmetrical portions. One of the asymmetrical portions is formed on the first sidewall of the gate structure, and the other asymmetrical portion is formed on the second sidewall of the gate structure. The semiconductor device includes a source region and a drain region formed in the semiconductor substrate and aligned with the outer edges of the asymmetrical portions of the gate spacer structure. In some embodiments, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.
    Type: Application
    Filed: December 23, 2021
    Publication date: July 28, 2022
    Inventors: Cheng-Hua LIN, Yan-Liang JI, Ching-Han JAN
  • Patent number: 10879389
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 29, 2020
    Assignee: MEDIATEK INC
    Inventors: Cheng-Hua Lin, Yan-Liang Ji, Chih-Wen Hsiung
  • Publication number: 20200119188
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Cheng-Hua LIN, Yan-Liang JI, Chih-Wen HSIUNG
  • Patent number: 10541328
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: January 21, 2020
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Hua Lin, Yan-Liang Ji, Chih-Wen Hsiung
  • Patent number: 10418480
    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 17, 2019
    Assignee: MediaTek Inc.
    Inventors: Chu-Wei Hu, Cheng Hua Lin
  • Patent number: 10396166
    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: August 27, 2019
    Assignee: MediaTek Inc.
    Inventors: Cheng Hua Lin, Yan-Liang Ji
  • Patent number: 10373949
    Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 6, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yan-Liang Ji, Cheng-Hua Lin, Chih-Chung Chiu
  • Publication number: 20190131450
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 2, 2019
    Inventors: Cheng-Hua LIN, Yan-Liang JI, Chih-Wen HSIUNG
  • Patent number: 10199496
    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate, a first well region, a second well region, a first gate structure, a first doped region, a second doped region, and a second gate structure. The first well region is formed in a portion of the semiconductor substrate. The second well region is formed in a portion of the first well region. The first gate structure is formed over a portion of the second well region and a portion of the first well region. The first doped region is formed in a portion of the second well region. The second doped region is formed in a portion of the first well region. The second gate structure is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Hua Lin, Yan-Liang Ji, Chih-Wen Hsiung
  • Patent number: 10177225
    Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 8, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yan-Liang Ji, Cheng-Hua Lin, Puo-Yu Chiang
  • Publication number: 20180240794
    Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.
    Type: Application
    Filed: August 15, 2017
    Publication date: August 23, 2018
    Inventors: Yan-Liang Ji, Cheng-Hua Lin, Chih-Chung Chiu
  • Patent number: 9825168
    Abstract: A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator. A first doped region is formed in the second well region, and a second doped region is formed in the first well region at a second side opposite the first side of the insulator. A gate structure is formed over the insulator, the first well region between the second well region and the insulator, and the second well region. An isolation element is formed in the semiconductor substrate, surrounding the first well region and the second well region. The first and second doped regions are formed with asymmetric configurations from a top view.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 21, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheng Hua Lin, Yan-Liang Ji