Patents by Inventor Cheng-hua Wang

Cheng-hua Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240421194
    Abstract: The present disclosure describes a semiconductor device having artificial field plates. The semiconductor device includes a first gallium nitride (GaN) layer on a substrate, an aluminum gallium nitride (AlGaN) layer on the first GaN layer, and a second GaN layer on the AlGaN layer. The first and second GaN layers includes different types of dopants. The semiconductor device further includes a gate contact structure in contact with the second GaN layer, first and second source/drain (S/D) contact structures in contact with the AlGaN layer, one or more artificial field plates between the gate contact structure and the first S/D contact structure. The first and second S/D contact structures are disposed at opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first and second S/D contact structures and above the AlGaN layer.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-An LAI, Pan Chieh Yu, Chih-Hua WANG, Chan-Hong CHERN, Cheng-Hsiang HSIEH
  • Patent number: 12164235
    Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Hua Wang, Kueilin Ho, Cheng Wei Sun, Zong-You Yang, Chih-Chun Chiang, Yi-Fam Shiu, Chueh-Chi Kuo, Heng-Hsin Liu, Li-Jui Chen
  • Publication number: 20240379820
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Patent number: 12130770
    Abstract: An apparatus for synchronous Ethernet comprises a processor, a field programmable gate array, a synchronizer, a physical layer implementor and a media accessing controller, wherein, the processor transmits a control data through a first transmission interface; the field programmable gate array receives the control data, generates a control instruction in accordance with the control data and transmits the control instruction through a second transmission interface; the synchronizer receives the control instruction and generates a synchronous clock in accordance with the control instruction; and each of the physical layer implementor and the media accessing controller receives and works in accordance with the synchronous clock and media accessing control protocol.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: October 29, 2024
    Assignee: ALPHA NETWORKS INC.
    Inventors: Pao-Kang Mo, Chien-Hua Wang, Cheng-Tai Tien, Shih-Feng Tseng
  • Publication number: 20240353241
    Abstract: A platform through-beam sensor device includes a transmitter module and a receiver module. A light emitted by a light-emitting element of the transmitter module is shaped into a light pattern range by a transmitter mask. A range of the light received by a light-receiving element of the receiver module is changed to a receiving range by a receiver mask. When the present invention is used, the transmitter module and the receiver module are respectively installed on two ends of a mechanical apparatus that move relative to each other. After determining a safety range of the relative movement of the two ends, a state that the light-receiving element falls into the light pattern range and the light-emitting element falls into the receiving range is set to be within the safety range. Upon exceeding the safety range, a flying platform is controlled to stop, thereby improving the safety of the flying platform.
    Type: Application
    Filed: August 25, 2023
    Publication date: October 24, 2024
    Applicant: Brogent Technologies Inc.
    Inventors: GUO-SEN LIAN, SHAO-HUA TSAI, CHENG-LIN HUANG, CHIH-HUANG WANG
  • Publication number: 20240347288
    Abstract: A key structure including a base plate, a thin film circuit, a display key, an elastic supporting member, and a lifting mechanism is provided. The thin film circuit is disposed on the base plate. The display key is disposed above the thin film circuit. The elastic supporting member is disposed between the display key and the thin film circuit. The lifting mechanism is disposed between the display key and the base plate.
    Type: Application
    Filed: November 21, 2023
    Publication date: October 17, 2024
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Cheng-Han Lin, Chuan-Hua Wang, Po-Yi Lee, Pin-Chueh Lin
  • Publication number: 20240345130
    Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Ting Chen, Cheng-Han Huang, Kuang-Hua Wang
  • Patent number: 12102237
    Abstract: An inflatable product includes an inflatable chamber and an elongated element. The inflatable chamber includes fusion portions. The elongated element is flexible, is disposed in the inflatable chamber, includes enlarged portions, and is connected to the inflatable chamber with the enlarged portions constrained by the fusion portions. The elongated element is in tension for controlling expansion of the inflatable chamber to a desired shape when the inflatable chamber is inflated to expand. The enlarged portions are constrained by the fusion portions to avoid separation of the elongated element from the inflatable chamber when the inflatable chamber is inflated to expand.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 1, 2024
    Assignee: Team Worldwide Corporation
    Inventors: Cheng-Chung Wang, Chien-Hua Wang, Yao-Hua Wang
  • Patent number: 12107149
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Publication number: 20240321973
    Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.
    Type: Application
    Filed: April 24, 2023
    Publication date: September 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Chih-Chien CHANG, Shen-De WANG, JIANJUN YANG, Wei Ta, Yuan-Hsiang Chang
  • Publication number: 20240290869
    Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 29, 2024
    Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
  • Patent number: 12066457
    Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Ting Chen, Cheng-Han Huang, Kuang-Hua Wang
  • Publication number: 20240266938
    Abstract: An improved switching power converting apparatus (10) includes a power converting circuit (102), a sampling circuit (104), a signal gain adjustment circuit (106), a frequency limiting circuit (108) and a pulse width modulation controller (110). The sampling circuit (104) is configured to detect the power converting circuit (102) to obtain a sampled signal (Vs) and transmit the sampled signal (Vs) to the signal gain adjustment circuit (106). The signal gain adjustment circuit (106) is configured to adjust the sampled signal (Vs) to obtain a control signal (Vcon) and transmit the control signal (Vcon) to the frequency limiting circuit (108). The pulse width modulation controller (110) is configured to control an operating frequency of the pulse width modulation controller (110) based on the control signal (Vcon).
    Type: Application
    Filed: February 2, 2023
    Publication date: August 8, 2024
    Inventors: Hao-Jen WANG, Cheng-Te TSAI, Hsiao-Hua CHI, Lien-Hsing CHEN, Chun-Ping CHANG, Liang-Jhou DAI
  • Patent number: 12045260
    Abstract: A method, system, and computer program product for data reorganization and logs reorganization. The method includes receiving, by one or more processing units, original data. The method also includes classifying, by the one or more processing units, the original data into different types based on a trained type classification model. The method also includes generating, by the one or more processing units, at least one severity for at least part of the original data based on a trained severity classification model, the at least part of the original data corresponding to at least one type. The method also includes outputting, by the one or more processing units, at least one message, the at least one message indicating the severity of the at least part of the original data.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: July 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Qing Li, Shan Gu, Shuang Men, Cheng Fang Wang, Li Hua Zhao, Qian Xia Song, Zhan Wei Wang
  • Publication number: 20240243114
    Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Mao-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Kuan-Lin Chen, Chun-Chieh Wang
  • Patent number: 12039093
    Abstract: An encrypted hard disk device is provided, including a near-field communication (NFC) sensing module, a processor, a storage unit, and a power switch. The NFC sensing module is configured to read a user identification (UID) of at least one sensor element. The processor is electrically connected to the NFC sensing module and the storage unit. The processor receives the UID and generates a control signal when the UID is approved. The power switch is electrically connected to the processor and the storage unit and maintains a conducting state according to the control signal and supplies power to the storage unit for accessing the storage unit.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: July 16, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Cheng-Yu Wang, Shao-Kai Liu, Yu-Hsiang Huang, Bo-Hua Yang
  • Patent number: 10372728
    Abstract: Systems, methods, and other embodiments are disclosed for identifying features within point cloud data. In one embodiment, point cloud data is read which represents multiple points of at least one point cloud in a multi-dimensional space. Each point in the point cloud data is defined by an attribute value quantifying an attribute of the point and a set of coordinates specifying a location of the point in the multi-dimensional space. The set of coordinates for each point is transformed into a space-filling distance value representing a distance along a space-filling curve. The points are sorted according to the space-filling distance values to generate a sorted order of the points. The points are traversed in the sorted order and output data points are derived, while traversing the points, based on a specified feature criterion. The output data points identify a feature within the at least one point cloud.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 6, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Michael Axel Ludwig Horhammer, Siva K. Ravada, Cheng-Hua Wang
  • Patent number: 10122583
    Abstract: Systems, methods, and other embodiments associated with aggregated network modeling with component network aggregation are described. In one embodiment, a method for modeling an aggregated network includes storing a first set of nodes associated with a first network and a first set of links associated with the first network, wherein each link in the first set of links connects a pair of nodes in the first set of nodes. A second set of nodes associated with a second network and a second set of links associated with the second network are also stored. A set of transfer links is stored. Each transfer link connects a node in the first network to a node in the second network. Metadata defines the aggregated network as the first set of nodes, the first set of links, the second set of nodes, the second set of links, and the set of transfer links.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: November 6, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Betsy George, Cheng-Hua Wang
  • Publication number: 20180081995
    Abstract: Systems, methods, and other embodiments are disclosed for identifying features within point cloud data. In one embodiment, point cloud data is read which represents multiple points of at least one point cloud in a multi-dimensional space. Each point in the point cloud data is defined by an attribute value quantifying an attribute of the point and a set of coordinates specifying a location of the point in the multi-dimensional space. The set of coordinates for each point is transformed into a space-filling distance value representing a distance along a space-filling curve. The points are sorted according to the space-filling distance values to generate a sorted order of the points. The points are traversed in the sorted order and output data points are derived, while traversing the points, based on a specified feature criterion. The output data points identify a feature within the at least one point cloud.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Michael Axel Ludwig HORHAMMER, Siva K. RAVADA, Cheng-Hua WANG
  • Publication number: 20160013987
    Abstract: Systems, methods, and other embodiments associated with aggregated network modeling with component network aggregation are described. In one embodiment, a method for modeling an aggregated network includes storing a first set of nodes associated with a first network and a first set of links associated with the first network, wherein each link in the first set of links connects a pair of nodes in the first set of nodes. A second set of nodes associated with a second network and a second set of links associated with the second network are also stored. A set of transfer links is stored. Each transfer link connects a node in the first network to a node in the second network. Metadata defines the aggregated network as the first set of nodes, the first set of links, the second set of nodes, the second set of links, and the set of transfer links.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 14, 2016
    Inventors: Betsy GEORGE, Cheng-Hua WANG