Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

Abstract: A blind lifting control module includes a transmitting wheel, an anti-backward unit and a driving unit disposed to a supporting unit. The transmitting wheel for connecting a blind reeled horizontal axle has ratchet portions respectively meshable with corresponding ratchet portions of an anti-backward wheel and a driving reel. A pull cord is reeled on the driving reel and has a free end passing through a thrust member and a hindering member, and is pulled to release the anti-backward wheel to permit lowering of a blind. The thrust member is turned by pulling of the pull cord to thrust the driving reel to mesh with the transmitting wheel for lifting the blind.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.

Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.

Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.

Abstract: A light-emitting device includes a patterned substrate, a buffer layer, an epitaxial layered unit, and at least one hole structure. The patterned substrate includes a supporting substrate having an upper surface, and a plurality of protrusions formed on the upper surface. Each of the protrusions includes a base and a cone sequentially stacked in such order on the upper surface. The cone is made of a material different from that of the supporting substrate. The buffer layer formed on a side wall surface of each of the protrusions and the upper surface of the supporting substrate exposed from the protrusions. The epitaxial layered unit is formed on the buffer layer opposite to the patterned substrate. The hole structure is disposed above a top end of at least one of the protrusions. A method for manufacturing the light-emitting device is also disclosed.

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

Abstract: A memory circuit includes a first and a second bit line coupled to a set of memory cells, a local input output circuit including a first and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal, a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal, a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation, and to electrically isolate the first and second data line from the first and second input signal during a read operation, and a first latch configured as a sense amplifier, during the read operation, and configured as a write-in latch, during the write operation.

Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Abstract: A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.