Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

Abstract: A memory circuit includes a memory array comprising a plurality of memory cells arranged over a plurality of word lines and along a bit line, and a controller operatively coupled to the memory array and comprising an RC detector. The RC detector is configured to advance a timing for a first tracking signal to fall, subsequently to a second tracking signal transitioning to rise and prior to a third tracking signal transitioning to rise. The first tracking signal is conducted through a first tracking line, the second tracking signal is provided to conduct through a second tracking line, and the third tracking signal is conducted through the second tracking line.

Abstract: A memory device has a memory cell operated in a first power domain having a first voltage level. A memory word line is connected to the memory cell, and a memory bit line is connected to the memory cell. A word line decoder circuit is operated in the first power domain, and a word line driver circuit is configured to receive a row address signal from the word line decoder circuit and output a word line enable signal to the memory word line. An IO circuit is connected to the memory bit line, and the IO circuit is operated in a second power domain having a second voltage level lower than the first voltage level. A tracking word line is connected to a tracking cell, and the tracking word line is configured to output a tracking cell enable signal in the first power domain. A tracking bit line is connected to the tracking cell, and the tracking bit line is configured to output a trigger signal in the first power domain to the IO circuit.

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Abstract: A memory device includes a memory cell and an amplifier. The memory cell is configured to store a first data bit. The amplifier is configured to generate a first data signal at a first node according to the first data bit, and configured to charge the first node according to a precharge signal. After the first node is charged according to the precharge signal, the amplifier is further configured to discharge the first node according to the precharge signal.

Abstract: A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.

Abstract: A memory device includes a memory cell in a first power domain of a first power supply voltage, a bit line coupled to the memory cell, and a write assist circuit. The write assist circuit includes an input, an output electrically couplable to the bit line in a write operation of the memory cell, an input circuit electrically coupled to the input, and an output circuit electrically coupled between the input circuit and the output. The input circuit is in a second power domain of a second power supply voltage different from the first power supply voltage, and the output circuit is in the first power domain.

Abstract: A memory circuit includes a first and second bit line coupled to a set of memory cells, a local input output (LIO) circuit coupled to the set of memory cells by the first and second bit line. The LIO circuit includes a first and second data line, and a first control circuit. The LIO circuit further includes a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation of the set of memory cells, and to electrically isolate the first and second data line from the first and second input signal during a read operation of the set of memory cells. The LIO circuit further includes a first latch circuit configured as a sense amplifier during the read operation, and configured as a write-in latch during the write operation.

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

Abstract: A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.

Abstract: An input/output circuit comprises a bypass circuit, a first latch, a second latch, a first transistor, and a second transistor. The bypass circuit is configured to directly receive a data signal and indirectly receive a write enable signal. The first latch is coupled between a first data line and a second data line. The second latch is operatively coupled to the first latch and configured to generate a data output signal based on a voltage level presented on the second data line. The first transistor is coupled to the first latch and gated by a sense enable signal. The second transistor is coupled to the first latch and gated by a clock signal. The first transistor and the second transistor are alternately activated in each of a plurality of operation modes of the input/output circuit.

Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.

Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.

Abstract: In some aspects of the present disclosure, a circuit in a first power domain is disclosed. In some aspects, the circuit in a first power domain includes a first enable-controlled logic gate coupled to a second circuit in a second power domain different from the first power domain. In some aspects, the circuit in a first power domain includes a feedback loop coupled to the first enable-controlled logic gate, the feedback loop including a first inverter and a second enable-controlled logic gate coupled to the first inverter. In some aspects, the circuit in a first power domain includes a second inverter coupled to the feedback loop.

Abstract: A memory circuit includes a first and a second bit line coupled to a set of memory cells, a local input output circuit including a first and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal, a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal, a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation, and to electrically isolate the first and second data line from the first and second input signal during a read operation, and a first latch configured as a sense amplifier, during the read operation, and configured as a write-in latch, during the write operation.

Abstract: In some aspects of the present disclosure, a dual rail circuit is disclosed. In some aspects, the dual rail circuit includes a first circuit in a first power domain. The first circuit comprises an input port and an output port. In some aspects, the dual rail circuit includes a second circuit in a second power domain different from the first power domain. The second circuit coupled to the input port of the first circuit and the output port of the first circuit.

Abstract: A vehicle may include a plurality of separate and distinct electrical busbars that are electrically isolated from each other. A device may include a polymer overmold material that mechanically couples the separate and distinct electrical busbars to each other in a single integrated multi-busbar unit, wherein the overmold material is provided to the busbars through an injection molding process. A device may include a flex printed circuit board having a plurality of sensors that is coupled to the single integrated multi-busbar unit, wherein the sensors are coupled to the distinct electrical busbars when the flex printed circuit board is coupled to the integrated busbar unit.

Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.