Abstract: A display driving device includes an emission circuit and a positive feedback circuit. The emission circuit is coupled to a first node. The emission circuit emits light according to a forward signal, a reverse signal, and a voltage level of the first node. The forward signal and the reverse signal are inversed phase of each other. The positive feedback circuit discharges the first node according to sweep signal.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.

Abstract: An electronic device including a circuit layer, an electronic element, a first flow-path structure and a fluid material is disclosed. The electronic element is disposed on the circuit layer and electrically connected to the circuit layer. The first flow-path structure includes a first flow path, and the electronic element is disposed in the first flow-path structure. The fluid material is disposed in the first flow path. The fluid material is used for performing heat exchange with the electronic element. The circuit layer includes an input hole and an output hole, and the fluid material enters the first flow path through the input hole and exits the first flow path through the output hole.

Abstract: A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.

Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes an upper surface; a plurality of exposed regions, formed in the semiconductor stack and exposing the upper surface; a lower protective layer, covering the exposed regions and the second semiconductor layer; a first reflective structure, formed on the second semiconductor layer and including a plurality of first openings on the second semiconductor layer; a second reflective structure, formed on the first reflective structure and electrically connected to the second semiconductor layer through the plurality of first openings; and an upper protective layer, formed on the second reflective structure; wherein the upper protective layer contacts and overlaps the lower protective layer on the exposed regions; wherein the first reflective structure and the

Abstract: An electronic device is provided and includes a first conductive structure, a second conductive structure, a third conductive structure, a first insulating layer, a second insulating layer, a conductive element, an electronic component, and a plurality of passive components. The first insulating layer is disposed between the first conductive structure and the second conductive structure, and the second insulating layer is disposed between the second conductive structure and the third conductive structure. The second conductive structure is electrically connected to the first conductive structure at a first position, and the third conductive structure is electrically connected to the second conductive structure at a second position, wherein a center point of the first position and a center point of the second position is misaligned along a normal direction of a surface of the first insulating layer.

Abstract: A variable resistor and a digital-to-analog converter are provided. The variable resistor includes a main resistor, a plurality of switches, and a plurality of redundancy resistors. The switches are respectively constituted by a plurality of non-volatile memory cells. The switches are coupled to the main resistor. The redundancy resistors are respectively coupled to the main resistor through the switches.

Abstract: A display apparatus is provided. The display apparatus includes a display module and multiple light-emitting driving circuits. Each of the light-emitting driving circuits includes a timing control circuit and a driving circuit. The timing control circuit receives multiple clock signals and a previous light-emitting timing signal to provide a light-emitting timing signal and an internal voltage. The driving circuit receives a first phase signal among multiple phase signals and the internal voltage to provide a light-emitting driving signal to the display module based on the first phase signal and the internal voltage. The phase signals all present disabled levels during a vertical blank period.

Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.

Abstract: A semiconductor structure can include a first substrate having a frontside and a backside opposite the frontside. The semiconductor structure can include devices on the frontside. The semiconductor structure can include first interconnect structures on the frontside and coupled to the devices. The semiconductor structure can include a heat distribution layer on the frontside and electrically isolated from the first interconnect structures, where the heat distribution layer includes a thermally conductive material. The semiconductor structure can include a second substrate coupled to the first substrate on the frontside. The semiconductor structure can include second interconnect structures on the backside and coupled to the devices.

Abstract: In one example in accordance with the present disclosure, an example computing device is disclosed. The example computing device includes a housing. The example computing device also includes a rotatable antenna disposed within the housing. The rotatable antenna is to rotate such that a direction of radiation is maintained in a single direction as the housing is to rotate.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings.

Abstract: The present disclosure provides a package device and a manufacturing method thereof. The package device includes an electronic device, a conductive pad having a first bottom surface, and a redistribution layer disposed between the conductive pad and the electronic device. The redistribution layer has a second bottom surface, and the conductive pad is electrically connected to the electronic device through the redistribution layer. The first bottom surface is closer to the electronic device than the second bottom in a normal direction of the electronic device.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a first semiconductor layer on an inner surface of a trench of a substrate; forming a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate; forming another first semiconductor layer on the second semiconductor layer on the inner surface of the trench of the substrate; forming another second semiconductor layer on the another first semiconductor layer on the inner surface of the trench of the substrate, in which the second semiconductor layer is sandwiched between the first semiconductor layer and the another first semiconductor layer, and the another first semiconductor layer is sandwiched between the second semiconductor layer and the another second semiconductor layer; and forming a third semiconductor layer on the another second semiconductor layer.

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.