Patents by Inventor Cheng Hung Shen

Cheng Hung Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211789
    Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: January 28, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
  • Publication number: 20240395698
    Abstract: A method includes following steps. A dielectric layer is formed over a substrate. A transition metal-containing layer is deposited on the dielectric layer. The transition metal-containing layer is patterned into a plurality of transition metal-containing pieces. The transition metal-containing pieces are sulfurized or selenized to form a plurality of semiconductor seeds. Semiconductor films are grown from semiconductor seeds. Transistors are formed on the semiconductor films.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
  • Publication number: 20240304461
    Abstract: A ceramic submount for a semiconductor device and a method for manufacturing the same are provided. The ceramic submount includes a ceramic core board, an electrode layer, and a solder unit. The electrode layer is disposed on one side of the ceramic core board. The solder unit includes a buffer containing layer and a soldering layer. A cross-section of the solder unit has an inversed-trapezoid shape. The buffer containing layer is disposed on a surface of the electrode layer. A receiving space is concavely formed on a top surface of the buffer containing layer, and the soldering layer is filled in the receiving space. The buffer containing layer surrounds the soldering layer.
    Type: Application
    Filed: December 26, 2023
    Publication date: September 12, 2024
    Inventors: CHENG-HUNG SHEN, SHIH-HAN WU, JHIH-WEI LAI, JIAN-YU SHIH, MING-YEN PAN, CHIA-SHUAI CHANG
  • Publication number: 20230378056
    Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
  • Patent number: 11784119
    Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 10, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
  • Publication number: 20230008409
    Abstract: A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.
    Type: Application
    Filed: March 23, 2022
    Publication date: January 12, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chen Han CHOU, Shu-Jui CHANG, Yen-Teng HO, Chia Hsing WU, Kai-Yu PENG, Cheng Hung SHEN, Chenming HU
  • Publication number: 20220319982
    Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.
    Type: Application
    Filed: August 23, 2021
    Publication date: October 6, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
  • Patent number: 8227924
    Abstract: Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Hung Shen, Tin-Hao Kuo, Chen-Cheng Kuo, Chen-Shien Chen, Yao-Chun Chuang
  • Publication number: 20120012985
    Abstract: Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.
    Type: Application
    Filed: July 13, 2010
    Publication date: January 19, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Hung Shen, Tin-Hao Kuo, Chen-Cheng Kuo, Chen-Shien Chen, Yao-Chun Chuang