Patents by Inventor CHENG-I CHU
CHENG-I CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12249592Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.Type: GrantFiled: January 18, 2022Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-De Chen, Cheng-I Chu, Yun Chen Teng, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 12211820Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.Type: GrantFiled: September 10, 2021Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-I Chu, Han-De Chen, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240387451Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Cheng-I Chu, Han-De Chen, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240379616Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Han-De Chen, Cheng-I Chu, Yun Chen Teng, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240332401Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240266285Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.Type: ApplicationFiled: April 18, 2024Publication date: August 8, 2024Inventors: Chen-Fong Tsai, Cheng-I Chu, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 12040382Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.Type: GrantFiled: May 17, 2021Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 11990404Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.Type: GrantFiled: July 21, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Fong Tsai, Cheng-I Chu, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20230019415Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.Type: ApplicationFiled: January 18, 2022Publication date: January 19, 2023Inventors: Han-De Chen, Cheng-I Chu, Yun Chen Teng, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20230010038Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.Type: ApplicationFiled: September 10, 2021Publication date: January 12, 2023Inventors: Cheng-I Chu, Han-De Chen, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20220359369Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.Type: ApplicationFiled: July 21, 2021Publication date: November 10, 2022Inventors: Chen-Fong Tsai, Cheng-I Chu, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20220262925Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.Type: ApplicationFiled: May 17, 2021Publication date: August 18, 2022Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 9296946Abstract: A method of manufacturing an oxynitride phosphor is revealed. A precursor is sintered under 0.1-1000 MPa nitrogen pressure for synthesis of an oxynitride phosphor. The general formula of the oxynitride phosphors is Ba3-XSi6O12N2:EuxBa3-XSi6O6N6:Eux or Ba3-XSi6O9N4:Eux (0.00001?x?5; 0.00001). Thus pure phosphor can be mass-produced.Type: GrantFiled: July 5, 2012Date of Patent: March 29, 2016Assignee: Formosa Epitaxy IncorporatedInventors: Cheng-I Chu, Ru-Shi Liu, Yu-Chih Lin, Chen-Hong Lee, Wei-Kang Cheng, Yi-Sheng Ting, Shyi-Ming Pan
-
Publication number: 20130009097Abstract: An oxynitride phosphor and a method of manufacturing the same are revealed. The formula of the oxynitride phosphor is Ba3-xSi6O12N2: Yx (0?x?1). Y is praseodymium (Pr) or terbium (Tb) used as a luminescent center. The oxynitride phosphor is synthesized by solid-state reaction. The oxynitride phosphor is excited by vacuum ultraviolet light with a wavelength range of 130 nm to 300 nm or ultraviolet to visible light with a wavelength range of 300 nm to 550 nm to emit light with a wavelength range of 400 nm to 700 nm. Moreover, the full-width at half-maximum of the emission spectrum is smaller than 30 nm. Thus the oxynitride phosphor is suitable for applications of backlights, plasma display panels and ultraviolet excitation. The oxynitride phosphor has higher application value.Type: ApplicationFiled: July 5, 2012Publication date: January 10, 2013Applicant: FORMOSA EPITAXY INCORPORATIONInventors: CHENG-I CHU, RU-SHI LIU, YU-CHIH LIN, CHEN-HONG LEE, WEI-KANG CHENG, YI-SHENG TING, SHYI-MING PAN
-
Publication number: 20130009096Abstract: An oxynitride phosphor and a method of manufacturing the same are revealed. The formula of the oxynitride phosphor is Ba3-x-ySi6O12N2:Cey, Eux (0?x?1, 0?y?1). Europium (Eu) and cerium (Ce) are luminescent centers. The oxynitride phosphor is synthesized by solid-state reaction. The oxynitride phosphor is excited by vacuum ultraviolet light with a wavelength range of 130 nm to 300 nm or ultraviolet to visible light with a wavelength range of 350 nm to 550 nm. The emission wavelength of the oxynitride phosphor is ranging from 400 nm to 700 nm. Thus the oxynitride phosphor can be applied to plasma display panels and ultraviolet (UV) excitation sources. The energy transfer occurs between Ce and Eu of the oxynitride phosphor and the oxynitride phosphor has a blue light emission peak and a green light emission peak. Thus color rendering index of the oxynitride phosphor is improved.Type: ApplicationFiled: July 5, 2012Publication date: January 10, 2013Applicant: FORMOSA EPITAXY INCORPORATIONInventors: CHENG-I CHU, RU-SHI LIU, YU-CHIH LIN, CHEN-HONG LEE, WEI-KANG CHENG, YI-SHENG TING, SHYI-MING PAN
-
Publication number: 20130009095Abstract: A method of manufacturing an oxynitride phosphor is revealed. A precursor is sintered under 0.1-1000 MPa nitrogen pressure for synthesis of an oxynitride phosphor. The general formula of the oxynitride phosphors is MxAyBzOuNv (0.00001?x?5; 0.00001?y?3; 0.00001?z?6; 0.00001?u?12; 0.00001?v?12). M is an activator or a mixture of activators. A is a bivalent element or a mixture of bivalent elements. B is a trivalent element, a tetravalent element, a mixture of trivalent elements or a mixture of tetravalent elements. O is a univalent element, a bivalent element, a mixture of univalent elements, or a mixture of bivalent elements. N is a univalent element, a bivalent element, a trivalent element, a mixture of univalent elements, a mixture of bivalent elements, or a mixture of trivalent elements. Thus pure phosphor can be mass-produced.Type: ApplicationFiled: July 5, 2012Publication date: January 10, 2013Applicant: FORMOSA EPITAXY INCORPORATIONInventors: CHENG-I CHU, RU-SHI LIU, YU-CHIH LIN, CHEN-HONG LEE, WEI-KANG CHENG, YI-SHENG TING, SHYI-MING PAN