Abstract: Boundary test circuit, memory and boundary test method are provided. The boundary test circuit may include a plurality of serially-connected wrapper boundary registers (WBRs) and a plurality of toggle circuits (TCs). Each WBR may include a first I/O for receiving an initial test signal and a second I/O for transmitting the initial test signal to the WBR at a succeeding stage. Each TC may include an input for receiving the initial test signal stored in a corresponding WBR, a control I/O for receiving a toggle signal, and an output for transmitting a real-time test signal to the integrated circuit. The toggle signal may be configured to control phase switching of the real-time test signal, and, depending on the toggle signal, the real-time test signal may have a phase identical or inverse to a phase of the initial test signal. This method improves the efficiency and flexibility of the boundary test.

Abstract: An integrated circuit with a through-silicon via (TSV) fault-tolerant circuit, a TSV fault tolerance method are disclosed. The IC may include a plurality of operational TSVs, a spare TSV, a plurality of fault-tolerance control modules each coupled to one of the plurality of operational TSVs and the spare TSV, and a decoder coupled to the fault-tolerance control modules. The fault-tolerance control modules may be configured to deactivate an operational TSV that is determined to be defective and activate the spare TSV based on a positioning code for the defective operational TSV from the decoder. The IC may reduce the defect rate in the fabrication of TSV-based three-dimensional (3D) IC chips.

Abstract: A memory test circuit apparatus and a method are provided. The method may include: compressing first test data output by a first storage array in a memory to generate first compressed data, compressing second test data output by a second storage array in the memory to generate second compressed data, compressing the first compressed data and the second compressed data to generate third compressed data, and outputting one of the first compressed data, the second compressed data and the third compressed data to determine a working condition of each of the first storage array and the second storage array. This method can provide not only a test result on a memory, but also a test result for individual storage array within the memory, which improves the efficiency of a circuit test.

Abstract: A fault detection system comprises a data server configured to collect parameters incoming from at least one apparatus, at least one fault-sensing module configured to generate an alarm signal if the parameter exceeds a predetermined specification, a monitoring module configured to restart the fault-sensing module if the fault-sensing module operates abnormally, and a remote controller configured to control the data server, the fault-sensing module, and the monitoring module.

Abstract: A dynamic fault detection method comprises the steps of acquiring a data curve from a machine, performing a waveform-recognition process to check if the data curve includes an effective waveform, performing a data-diagnosing process to check if the value of the effective waveform in an effective region falls outside a predetermined range, and generating an alarm signal if the value of the effective waveform in the effective region falls outside the predetermined range. The waveform-recognition process comprises the steps of checking if the data curve includes a first segment, a second segment and a third segment sandwiched between the first segment and the second segment, and checking if the length of the third segment is larger than a predetermined value. The waveform is determined to include the effective waveform if the checking results are true.

Abstract: A system for detecting a plasma reaction and a method for using the same are provided. When the plasma reaction changes its reaction power, a lightness variation accompanies the power change. The system comprises a sensing device with a resistance that the resistance of the sensing device will be changed in response to the lightness variation; thereby the system can detect the status of the plasma reaction.

Abstract: The present invention provides a method to form a self-aligned MOS transistor with a gate capped by a metal silicide layer. The gate has a larger surface area and a lower resistance, so this method is suitable as the feature size of integral circuits scale down. In this method, the primary step is to deposit a selective dielectric layer, such as polysilicon germanium layer, on the top of a gate to increase the surface area of the gate. Then, a metal silicide layer is formed on the surface of the dielectric layer to decrease the resistance of the gate. Therefore, comparing to conventional methods, a gate formed by the present method has a larger contacting area and is more ease to connect to a conductive line, so that the performance of a MOS transistor can be improved.

Abstract: The present invention provides a method for fabricating a metal-oxide-semiconductor (MOS) transistor on the surface of a semiconductor wafer. The present method first forms a stacked structure comprising a dielectric layer, a doped polysilicon layer, and a sacrificial layer, respectively, in the active area of the surface of the semiconductor wafer. Next, two lightly doped drains are then formed adjacent to the stacked structure. A spacer is then formed around the stacked structure, followed by an ion implantation process to form a source and drain of the MOS transistor. Then, the sacrificial layer is removed to form a trough with the spacer and the doped polysilicon layer. A self-aligned silicide (salicide) process is then performed to form a silicide layer on the surface of the source, drain, and doped polysilicon layer. Finally, a tungsten (W) layer is formed on the surface of each silicide layer and filling the trough to complete the fabrication of the MOS transistor according to the present invention.

Abstract: A chemical mechanical polishing slurry comprising: a nitric acid solution; a weak acid solution, wherein mollar concentration of for weak acid acqeous solution is less than mollar concentration of for nitric acid acqeous solution; and an abrasive. Also, a method for polishing a substrate including at least one metal layer, comprising: mixing a nitric acid solution, a weak acid solution, an abrasive and a solvent to form a chemical mechanical polishing slurry; applying for chemical mechanical polishing slurry to for substrate; and bringing a pad into contact with for substrate and moving for pad in relation to for substrate to remove a portion of for metal layer.

Abstract: A method for forming shallow junction, at least includes following steps: provides a substrate; forms a dielectric layer and a conductor layer in sequence on the substrate; removes part of the conductor layer and part of the dielectric layer to form a gate on the substrate; forms a spacer on the sidewall of the gate; forms a poly-silicon-germanium layer on the bare surface of the substrate and the top of the gate; implants numerous ions into the poly-silicon-germanium layer and forms a metal layer on both the poly-silicon-germanium layer and the spacer; performs a thermal process; and removes residual the metal layer. Whereby, the sequences for ions implantation and formation of poly-silicon-germanium layer are exchangeable.

Abstract: A structure for being used in measuring a capacitance of a capacitor is provided. The structure includes a plurality of input terminals having an operating voltage and an operating frequency, a first quasi-inverting circuit having a first parasitic capacitor for generating a first current and electrically connected with the input terminals, a second quasi-inverting circuit having a second parasitic capacitor and a first reference capacitor for generating a second current and electrically connected with the first quasi-inverting circuit, and a third quasi-inverting circuit having the capacitor, a third parasitic capacitor and a second reference capacitor for generating a third current and electrically connected with the quasi-inverting circuit.

Abstract: A low dielectric constant nanotube, which can be used in the damascene process, and the fabrication method for a non-selective and a selective nanotube thin film layer are described. The non-selective deposition of the nanotube thin film layer includes forming a catalytic layer on the substrate followed by chemical vapor depositing a nanotube thin film layer on the catalytic layer. The selective deposition of the nanotube thin film layer includes forming a catalytic layer on the substrate followed by patterning the catalytic layer. A patterned photoresist layer can also form on the substrate, followed by forming multiple of catalytic layers on the photoresist layer and on the exposed substrate respectively. The photoresist layer and the overlying catalytic layer are removed. Thereafter, a nanotube layer is formed on the patterned catalytic layer by chemical vapor deposition.

Abstract: A process of forming a low dielectric constant (low k) material is disclosed. The process of the present invention comprises introducing silane (SinH2n+2) and fluorocarbon (CmF2m+2) gases, where n=1 to 3 and m=1 to 3, into a chemical vapor deposition (CVD) chamber, thus forming a low dielectric material layer on a substrate having semiconductor devices by the CVD process. An in situ Argon annealing process is then performed in the chamber. The process of the present invention produces a layer having a dielectric constant of 2.5 and good thermal stability.

Abstract: A method of fabricating a DRAM capacitor. A silicon germanium layer is formed on a lower electrode of the capacitor. The silicon germanium layer is oxidized to form a segregated grained germanium layer and a silicon oxide layer where the segregated grained germanium is distributed on the lower electrode. The silicon oxide layer is then removed. Using the segregated grained germanium as a hard mask, the lower electrode is etched to a depth to form a multi-cylinder structure. The segregated grained germanium is then removed. A capacitor dielectric layer and an upper electrode are successively formed on the multi-cylinder structure.